Abstract: A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme.

Abstract: A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme.

Abstract: A digital transcoder system is presented for receiving data bit streams with a first bit rate (R1) and outputting a data bit stream with a second bit rate (R2) which differs from the first bit rate (R1), and in particular is reduced relative thereto. This transcoder system has a decoder device (10) on its input side and a coder device (20) on its output side, the latter consisting of a series circuit of a quantizer (21) for requantizing the data dequantized in the decoder device (10), with a requantization factor (Q2), also with a subsequent VLC coder (22) and an output buffer (23). Establishing the second bit rate (R2) requires that the requantization factor of the quantizer (21) be changed, with reference to macro-blocks, according to the specification of a certain calculational formula.

Abstract: A digital transcoder system is presented for receiving data bit streams with a first bit rate (R1) and outputting a data bit stream with a second bit rate (R2) which differs from the first bit rate (R1), and in particular is reduced relative thereto. This transcoder system has a decoder device (10) on its input side and a coder device (20) on its output side, the latter consisting of a series circuit of a quantizer (21) for requantizing the data dequantized in the decoder device (10), with a requantization factor (Q2), also with a subsequent VLC coder (22) and an output buffer (23). Establishing the second bit rate (R2) requires that the requantization factor of the quantizer (21) be changed, with reference to macro-blocks, according to the specification of a certain calculational formula.

Abstract: A digital transcoder system is presented for receiving data bit streams with a first bit rate (R1) and outputting a data bit stream with a second bit rate (R2) which differs from the first bit rate (R1), and in particular is reduced relative thereto. This transcoder system has a decoder device (10) on its input side and a coder device (20) on its output side, the latter consisting of a series circuit of a quantizer (21) for requantizing the data dequantized in the decoder device (10), with a requantization factor (Q2), also with a subsequent VLC coder (22) and an output buffer (23). Establishing the second bit rate (R2) requires that the requantization factor of the quantizer (21) be changed, with reference to macro-blocks, according to the specification of a certain calculational formula.