Abstract: A method for determining an actual geometry of a track by a track inspection vehicle which is movable on the track, wherein reference points positioned in a lateral environment of the track are automatically recorded by a non-contacting recording system arranged on the track inspection vehicle and their respective actual distance from the track is determined. A three-dimensional trajectory of the track is recorded by an inertial measuring system arranged on the track inspection vehicle, wherein the trajectory is divided by a computing unit into trajectory sections each having a section starting point related to a first reference point and a section end point related to a second reference point, wherein a virtual longitudinal chord is defined for each trajectory section in relation to the assigned reference points, and wherein actual distances between the trajectory and the respectively defined longitudinal chord are calculated for each trajectory section.

Abstract: An integrated circuit that may be employed as a smart switch is described herein. In accordance with one embodiment the integrated circuit includes a power transistor coupled between a supply pin and an output pin and further includes a control circuit configured to trigger a switch-on and a switch-off of the power transistor in accordance with an input signal. The control circuit is configured to trigger a switch-off of the power transistor when a load current passing through the power transistor is at or above a predetermined current and a supply voltage received at the supply pin is at or below a predetermined threshold voltage.

Abstract: An integrated circuit that may be employed as a smart switch is described herein. In accordance with one embodiment the integrated circuit includes a power transistor coupled between a supply pin and an output pin and further includes a control circuit configured to trigger a switch-on and a switch-off of the power transistor in accordance with an input signal. The control circuit is configured to trigger a switch-off of the power transistor when a load current passing through the power transistor is at or above a predetermined current and a supply voltage received at the supply pin is at or below a predetermined threshold voltage.

Abstract: Examples disclosed herein involve integrated circuit chip arrangements. An example integrated circuit (IC) package may include a first semiconductor chip that includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second semiconductor chip mounted within a housing of the IC package. The second semiconductor chip may include a second MOSFET and a control circuit configured with a first driver for the first MOSFET and a second driver for the second MOSFET. The first semiconductor chip may be mounted to the second semiconductor chip opposite a base of the IC package.

Abstract: Devices and methods comprising a switch and an overload detection are disclosed. When an overload detection is detected, a first retry scheme followed by a second retry scheme different from the first retry scheme may be applied. If the overload condition persists, the switch may be disabled.

Abstract: A semiconductor device includes at least one wiring layer disposed on a semiconductor body, a field effect transistor integrated in the semiconductor body, the field effect transistor having a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body, a first circuit integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit integrated in the semiconductor body and remote from the first circuit. The semiconductor device further includes a first additional trench formed in the semiconductor body and at least one conductive pad formed in the at least one wiring layer. The first additional trench includes at least one connecting line which electrically connects the first circuit and the second circuit. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract: Disclosed is a method for producing a recombinant protein of interest, the method being characterized in by the following steps: (a) providing a fusion protein comprising an Npro autoprotease moiety and a protein of interest moiety in inclusion bodies, (b) solubilizing the inclusion bodies, (c) allowing the fusion protein to be cleaved by the Npro autoprotease moiety under chaotropic conditions, wherein the recombinant protein of interest is cleaved from the fusion protein and wherein the recombinant protein of interest is not yet renatured or simultaneously renatured, and (d) recovering the protein of interest, optionally including a renaturing step for the protein of interest.

Abstract: Devices and methods comprising a switch and an overload detection are disclosed. When an overload detection is detected, a first retry scheme followed by a second retry scheme different from the first retry scheme may be applied. If the overload condition persists, the switch may be disabled.

Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract: Disclosed is a method for producing a recombinant protein of interest which is characterised by the following steps: (a) providing a first part of an Npro autoprotease and providing a second part of an Npro autoprotease, wherein said second part is fused by a peptidic bond to a protein of interest but said second part alone does not exhibit a proteolytic activity, and wherein complementation of said first part with the second part forms an autoproteolytically active Npro autoprotease, (b) contacting the first part of the Npro autoprotease with the second part of the Npro autoprotease so that an autoproteolytically active Npro autoprotease is formed and the protein of interest fused by the peptidic bond to the second part of the Npro autoprotease is proteolytically cleaved off the second part of the Npro autoprotease at the peptidic bond, and (c) recovering the protein of interest.

Abstract: Disclosed is a method for producing a recombinant protein of interest, the method being characterised in by the following steps: (a) providing a fusion protein comprising an Npro autoprotease moiety and a protein of interest moiety in inclusion bodies, (b) solubilising the inclusion bodies, (c) allowing the fusion protein to be cleaved by the Npro autoprotease moiety under chaotropic conditions, wherein the recombinant protein of interest is cleaved from the fusion protein and wherein the recombinant protein of interest is not yet renatured or simultaneously renatured, and (d) recovering the protein of interest, optionally including a renaturing step for the protein of interest.

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract: An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.

Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.

Abstract: An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.

Abstract: Disclosed is an affinity matrix comprising a solid phase and an affinity ligand comprising peptide bonds coupled to this solid phase, wherein the affinity ligand comprising peptide bond is selected from the following group of ligands: a) peptides comprising the formula X1X2X3X4, wherein X1 to X4 are amino acid residues and at least two of X1 to X4 is W, Y or F; b) peptides comprising the formula X5X6X7X8, wherein X5 to X8 are amino acid residues, at least one of X5 to X8 is W, and at least one of X5 to X8 is E or D; and c) poly-amino acids consisting of an amino acid monomer of the group consisting of R, K, E and D and an amino acid monomer of the group consisting of Y, F and W, preferably poly-KY, poly-KF, poly-KW, poly-RY, poly-RF, poly-RW, poly-EY, poly-DY, poly-EF, poly-EW, poly-DF and poly-DW, with the proviso that the peptides according to a) and b) have a maximum length of 35 amino acid residues and that the poly-amino acids according to c) have a minimum length of 20 amino acid residues.

Abstract: A system for minimizing signals for video data communication is provided. The system comprises a first interface for selecting at least one video signal for transmission via a video data vector based on a data enable signal and a second interface for outputting at least one video signal from the video data vector based on the data enable signal.

Abstract: The invention relates to a process for the recombinant production of a heterologous polypeptide of interest by cultivating a bacterial host cell transformed with an expression vector comprising a nucleic acid molecule encoding a fusion polypeptide wherein (a) the amino-proximal fusion partner is an autoprotease Npro comprising the replacement(s) by glutamic acid of one or more cysteines at positions corresponding to the positions 112, 134, and 138 of the autoprotease Npro of classical swine fever virus and (b) the carboxyl-proximal fusion partner is an heterologous polypeptide of interest fused to the autoprotease Npro so that it is capable of being cleaved from the fusion polypeptide by autoprotease Npro autoproteolytic activity, said process comprising (i) cultivating the transformed host cell under conditions permitting the expression of the fusion polypeptide and the formation of corresponding cytoplasmic inclusion bodies, (ii) isolating the inclusion bodies from the host cell, (iii) solubilizing the isol