Abstract: Exothermic and/or endothermic chemical reactions in combination with phase change materials can produce output temperature(s) within strict tolerances without requiring expensive and complicated external equipment to generate and maintain an output temperature. Similarly, an exothermic phase change material, which generates heat as a consequence of crystallizing a supercooled liquid, can generate heat at a constant temperature, without requiring expensive and complicated external equipment, as a consequence of the liquid form of the exothermic phase change material being in equilibrium with the solid form of the exothermic phase change material. Numerous biological and chemical processes and/or diagnostic devices require a constant temperature or temperatures for set periods of time.

Abstract: A construction wall system comprising, an inner rigid panel and an outer rigid panel of rectangular shape and defining length and breadth dimensions and defining side edges on either side and end edges on ends. The panels being spaced apart from one another with plurality of intermediate junction strips secured between the inner and outer panels, in parallel spaced apart relation, at spaced intervals. A plurality of end junction strips are secured between said inner and outer panels adjacent opposite side edges thereof, and spaced inwardly from the side edges to define junction channels along the side edges between the inner and outer panels. A plurality of spacer strips are secured between the inner and outer panels the spacer strips being spaced inwardly relative to the end edges of the panels to define end junction channels between the inner and outer panels.

Abstract: An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18).

Abstract: An integrated circuit chip comprises a digital signal processor core (12) formed on a portion of the surface area of the chip (10). The digital signal processor (12) has a read only memory (14), a random access memory (16), a register file (18), an arithmetic logic unit (20) and a multiplier circuit (22). The remaining surface area of the integrated circuit chip (10) forms a user-definable circuitry area (24) which is used to form added circuitry to interface the digital signal processor (12) with other components of an integrated data processing system. The circuits formed in the user-definable circuitry area (24) are coupled to other integrated circuit chips through universal input/output bond pads (28). In one embodiment of the present invention, parallel module testing multiplexers (26) are added to aid in the testing of the digital signal processor (12) and the added circuits formed in the user-definable circuitry area (24).

Abstract: An output buffer includes a pair of P-channel transistors and two cascode pull-down N-channel transistors to drive an output node. The output pull-up transistor has the gate thereof connected through a P-channel control transistor to an input driving signal. The control signal is isolated from the output node by a P-channel transistor which only conducts during overvoltage conditions. During normal operation, the control transistor is maintained in a conductive state to allow the gate of the output pull-up transistor to be pulled high and low. During an overvoltage condition, the P-channel transistor connected between the output node and the control transistor is turned on in order to effectively turn off the control transistor. The P-channel transistors in the output buffer are floating well-type transistors with the wells thereof tied to a switched voltage that is either the supply voltage during the normal operating mode or the output node during overvoltage conditions.

Abstract: A current controlled ring oscillator is utilized in a phase locked loop system. The ring itself is comprised of lateral pnp current sources and Schottky clamped npn transistors to provide a frequency range of 4 megahertz at 50 microamp drive to 43 megahertz at 1 milliamp drive. The frequency of the ring oscillator is varied by varying the current injected into the ring.