Patents by Inventor Bernhard Laubli
Bernhard Laubli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11991273Abstract: Key management for encrypted data. A node, such as a storage device, obtains a shared key to be used in cryptographic operations. The obtaining includes using an identifier of another node, such as a host of the computing environment, and a unique identifier of the shared key to obtain the shared key. The obtained shared key is then used in one or more cryptographic operations.Type: GrantFiled: September 4, 2018Date of Patent: May 21, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jacob L. Sheppard, Igor Popov, Roger G. Hathorn, Bernhard Laubli
-
Patent number: 10606780Abstract: A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.Type: GrantFiled: February 21, 2018Date of Patent: March 31, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Publication number: 20200076585Abstract: Key management for encrypted data. A node, such as a storage device, obtains a shared key to be used in cryptographic operations. The obtaining includes using an identifier of another node, such as a host of the computing environment, and a unique identifier of the shared key to obtain the shared key. The obtained shared key is then used in one or more cryptographic operations.Type: ApplicationFiled: September 4, 2018Publication date: March 5, 2020Inventors: Jacob L. Sheppard, Igor Popov, Roger G. Hathorn, Bernhard Laubli
-
Patent number: 10579579Abstract: An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.Type: GrantFiled: August 20, 2018Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Publication number: 20180357196Abstract: An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.Type: ApplicationFiled: August 20, 2018Publication date: December 13, 2018Inventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Patent number: 10083144Abstract: An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.Type: GrantFiled: September 30, 2015Date of Patent: September 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Patent number: 10049050Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: July 25, 2016Date of Patent: August 14, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
-
Publication number: 20180181516Abstract: A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.Type: ApplicationFiled: February 21, 2018Publication date: June 28, 2018Inventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Patent number: 9928196Abstract: A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.Type: GrantFiled: September 30, 2015Date of Patent: March 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Patent number: 9811336Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.Type: GrantFiled: October 1, 2014Date of Patent: November 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles S. Cardinell, Bernhard Laubli, Timothy J. Van Patten
-
Publication number: 20170091135Abstract: An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Publication number: 20170091132Abstract: A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Charles S. Cardinell, Roger G. Hathorn, Steven E. Klein, Bernhard Laubli
-
Patent number: 9436607Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: May 14, 2015Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
-
Patent number: 9075720Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: GrantFiled: October 4, 2010Date of Patent: July 7, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
-
Publication number: 20150019839Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.Type: ApplicationFiled: October 1, 2014Publication date: January 15, 2015Inventors: Charles S. Cardinell, Bernhard Laubli, Timothy J. Van Patten
-
Patent number: 8935511Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.Type: GrantFiled: October 11, 2010Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: Charles S. Cardinell, Bernhard Laubli, Timothy J. Van Patten
-
Patent number: 8850262Abstract: An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.Type: GrantFiled: October 12, 2010Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Timothy J. Van Patten
-
Publication number: 20120089815Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.Type: ApplicationFiled: October 11, 2010Publication date: April 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles S. Cardinell, Bernhard Laubli, Timothy J. Van Patten
-
Publication number: 20120089861Abstract: An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.Type: ApplicationFiled: October 12, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Timothy J. Van Patten
-
Publication number: 20120084514Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten