Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.

Abstract: A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.

Abstract: A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.

Abstract: A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract: A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a transistor comprising a metal gate disposed on a gate dielectric that is disposed on a substrate, and a source/drain region disposed adjacent a channel region of the transistor. The source/drain region comprises a source/drain extension comprising a vertex point, wherein a top surface of the channel region is substantially planar with the vertex point.

Abstract: A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.

Abstract: A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

Abstract: A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.

Abstract: A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A source region and a drain region are isotropically etched in the substrate. A Silicon Germanium alloy is doped in situ with Boron in the source region and in the drain region. Silicon is deposited on the Silicon Germanium alloy. Nickel is deposited on the Silicon. A Nickel Silicon Germanium silicide layer is formed on the Silicon Germanium alloy. A Nickel Silicon silicide layer is formed on the Nickel Silicon Germanium silicide layer.

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

Abstract: Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer layer.

Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

Abstract: A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle ? of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Abstract: A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage.