Patents by Inventor Berry Anthony Johannus Buter
Berry Anthony Johannus Buter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10732577Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.Type: GrantFiled: July 31, 2019Date of Patent: August 4, 2020Assignee: NXP B.V.Inventors: Hao Fan, Michiel Pertijs, Berry Anthony Johannus Buter
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Publication number: 20200073334Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.Type: ApplicationFiled: July 31, 2019Publication date: March 5, 2020Inventors: Hao Fan, Michiel Pertijs, Berry Anthony Johannus Buter
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Patent number: 10254177Abstract: Disclosed is an integrated circuit temperature sensor including a first capacitor having a first capacitance relative to a temperature, a second capacitor a second capacitance relative to the temperature, and a controller configured to determine a ratio of the first capacitance to the second capacitance in order to determine a temperature of a region of the integrated circuit.Type: GrantFiled: September 14, 2016Date of Patent: April 9, 2019Assignee: NXP B.V.Inventor: Berry Anthony Johannus Buter
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Publication number: 20180073938Abstract: Disclosed is an integrated circuit temperature sensor including a first capacitor having a first capacitance relative to a temperature, a second capacitor a second capacitance relative to the temperature, and a controller configured to determine a ratio of the first capacitance to the second capacitance in order to determine a temperature of a region of the integrated circuit.Type: ApplicationFiled: September 14, 2016Publication date: March 15, 2018Inventor: Berry Anthony Johannus BUTER
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Patent number: 8451161Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (?1) to a first input voltage (±Vm) and on a second clock signal (?2) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negative rType: GrantFiled: October 5, 2009Date of Patent: May 28, 2013Assignee: Integrated Device Technology, Inc.Inventors: Berry Anthony Johannus Buter, Hans Van de Vel
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Patent number: 8390372Abstract: A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.Type: GrantFiled: March 17, 2011Date of Patent: March 5, 2013Assignee: NXP, B.V.Inventors: Berry Anthony Johannus Buter, Hans Van de Vel
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Patent number: 8362939Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.Type: GrantFiled: June 11, 2009Date of Patent: January 29, 2013Assignee: Integrated Device Technology, Inc.Inventors: Berry Anthony Johannus Buter, Hans Van De Vel
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Patent number: 8350743Abstract: Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.Type: GrantFiled: April 13, 2011Date of Patent: January 8, 2013Assignee: Integrated Device Technology, IncInventors: Hans van de Vel, Berry Anthony Johannus Buter
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Publication number: 20120068766Abstract: A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.Type: ApplicationFiled: March 17, 2011Publication date: March 22, 2012Applicant: NXP B.V.Inventors: Berry Anthony Johannus Buter, Hans Van de Vel
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Publication number: 20110254717Abstract: Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.Type: ApplicationFiled: April 13, 2011Publication date: October 20, 2011Applicant: NXP B.V.Inventors: Hans VAN DE VEL, Berry Anthony Johannus BUTER
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Publication number: 20110193736Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (4)1) to a first input voltage (±Vm) and on a second clock signal (?1) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negativeType: ApplicationFiled: October 5, 2009Publication date: August 11, 2011Applicant: NXP B.V.Inventors: Berry Anthony Johannus Buter, Hans Van deVel
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Publication number: 20110095930Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.Type: ApplicationFiled: June 11, 2009Publication date: April 28, 2011Applicant: NXP B.V.Inventors: Berry Anthony Johannus Buter, Hans Van De Vel