Abstract: A method of reducing bit error rate in a PAM4 clock data recovery circuit is described. The method includes determining a first target value of a slicing level, sweeping down from an upper voltage threshold to determine a first reference voltage value, and detecting a first filtered analog output associated with the first reference voltage value. The method also includes sweeping up from a lower voltage threshold to determine a second reference voltage value and detecting a second filtered analog output associated with the second reference voltage value. The first reference voltage value and the second reference voltage value are averaged to determine a calculated threshold value.

Abstract: A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value.

Abstract: A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value.