Patents by Inventor Betty H. Yeung

Betty H. Yeung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9054111
    Abstract: An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: June 9, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianwen Xu, Lizabeth Ann A. Keser, Goerge R. Leal, Betty H. Yeung
  • Patent number: 7989951
    Abstract: An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: August 2, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Betty H. Yeung, David J. Dougherty
  • Patent number: 7950144
    Abstract: A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 31, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshmi N. Ramanathan, George R. Leal, Douglas G. Mitchell, Betty H. Yeung
  • Publication number: 20100252919
    Abstract: An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation.
    Type: Application
    Filed: April 7, 2009
    Publication date: October 7, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jianwen Xu, Lizabeth Ann Keser, Goerge R. Leal, Betty H. Yeung
  • Publication number: 20100142168
    Abstract: An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Betty H. Yeung, David J. Dougherty
  • Publication number: 20090271980
    Abstract: A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Inventors: Lakshmi N. Ramanathan, George R. Leal, Douglas G. Mitchell, Betty H. Yeung