Abstract: A sensor system includes a power harvesting subsystem, a control subsystem, a sensor subsystem and a communication subsystem. Electromechanical systems generate and dissipate multiple forms of waste energy as a by-product of system operation. Waste energy in the system may lead to destructive side effects which adversely affect the life of system elements. The sensor system is powered above a predetermined level and communicates the sensed information to a remote processor for system diagnosis.

Abstract: A state machine has specific states to boot a microprocessor and retrieve data from the microprocessor's memories while the microprocessor is running, but with operation temporarily suspended under control of the state machine. The state machine is programmed after it is installed on a circuit board with the microprocessor. The state machine is connected to a standard bus and through its specific states provides an interface to the microprocessor as well as the instructions for booting the microprocessor when the microprocessor is powered up.

Abstract: An interface between a host and a bus includes label generator and a memory. The label generator responds to bus label signals from the bus, for providing label signals. The memory responds to bus signals from the bus, for providing memory host signals to the bus. The memory further reponds to the label signals from the label generator for storing the label signals as label memory signals. The memory further responds to host signals from the host, either for providing memory bus signals to the host when the host reads memory bus information from the memory, or for providing said label memory signals to the host when the host reads label memory information from the memory.

Abstract: A signal selection system has input thereto a plurality of redundant input signals having varying values along with signals indicative of the validity of the plurality of input signals, comparison logic compares all possible pairwise combinations of the input signals to determine which input signal in each of the input signal pairs has the greater value or to determine if the input signals in each pair have equal values. Mid value selection logic determines which one or more of the values of the input signals from the plurality of valid input signals are to be used to determine the output signal according to a mid value selection criterion. The selection logic has a plurality of combinational logic elements arranged to execute predetermined Boolean logic equations in determining which one or more of the values of the input signals from the plurality of valid inputs are to be used to determine the output signal according to the predetermined mid value selection criterion.

Abstract: An interrupt is provided to a signal processor having a non-maskable interrupt input, in response to the detection of a request for transfer to backup software. The signal processor provides a transfer signal to a transfer mechanism only after completion of the present machine cycle. Transfer to the backup software is initiated by the transfer mechanism only upon reception of the transfer signal.

Abstract: Data is communicated between redundant channels formatted in blocks having an initial command word followed by a destination code, starting address and a variable number of data words including a word count. The blocks are transmitted between each channel and all of the channels over cross-channel data links, each channel receiving the data blocks and determining the validity thereof by counting the number of data words received and comparing that number to the word count transmitted for that block. An interrupt signal indicative of invalidity of a block is provided in the event of a miscompare. A stop address is generated for each block received for storage at the start address. A memory address is generated for each valid word received for storage in sequence starting immediately after the start address. The next block received has its start address placed immediately at the end of the previously received block.

Abstract: Tasks may be planned for execution on a single processor or are split up by the designer for execution among a plurality of signal processors. The tasks are modeled using a design aid called a precedence graph, from which a dependency table and a prerequisite table are established for reference within each processor. During execution, at the completion of a given task, an end of task interrupt is provided from any processor which has completed a task to any and all other processors including itself in which completion of that task is a prerequisite for commencement of any dependent tasks. The relevant updated data may be transferred by the processor either before or after signalling task completion to the processors needing the updated data prior to commencing execution of the dependent tasks. Coherency may be ensured, however, by sending the data before the interrupt.

Abstract: Arbitration access to an IOC's RAM between the IOC's I/O bus and a signal processor is accomplished by always granting the signal processor access to the IOC's RAM for one machine cycle and disallowing any signal processor operations which would otherwise permit preemptive demand access to memory for more than one machine cycle. The signal processor's activity is then monitored for detecting the signal processor engaged in an activity which does not presently require access to the IOC's RAM and which will occupy the signal processor in a non-memory access activity for a predictable period of time. The IOC's I/O bus is then granted access to the IOC's RAM for a period of time less than the predicted period. In addition to this transparency feature, the present invention may be used in a context of a unique method of transferring data between sensors and actuators on one side of the IOC and the signal processor on the other side.

Abstract: A plurality of n-dimensional modular entities are internally interconnected via as many as n duel port random access memory devices (DPRs), each memory device dedicated solely to the interchange of information between two modular entities in an n-dimensional lattice of modular entities. One or more of the modular entities may itself be a separate multiprocessor architecture.

Abstract: A miscomparison between a channel's configuration data base and a voted system configuration data base in a redundant channel system having identically operating, frame synchronous channels triggers autoequalization of the channel's historical signal data bases in a hierarchical, chronological manner with that of a correctly operating channel. After equalization, symmetrization of the channel's configuration data base with that of the system permits upgrading of the previously degraded channel to full redundancy. An externally provided equalization command, e.g., manually actuated, can also trigger equalization.

Abstract: A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

Abstract: A synchronizer for use in synchronizing individual signal processors in a multi-channel system is disclosed. Each synchronizer has a counter for counting its associated processor's clock pulses and, upon reaching a selected count, providing a counter frame output signal at an output thereof for use by each of the other synchronizers in the system. Each synchronizer has a voter responsive to counter output signals from each of the other synchronizers, and from itself as well, at input ports thereof. Each synchronizer's voter provides a frame sync (macro sync) pulse in each counter frame after receiving a selected number of counter frame output signals from any of the synchronizers in the system.

Abstract: An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes a wraparound receive memory to ensure coherency with very little processor overhead.

Abstract: A coherent interface between one or more asynchronous busses and one or more channels in which only one channel is permitted to communicate with a bus at a time is disclosed.

Abstract: An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes both a wraparound receive and transmit memory to ensure coherency with very little processor overhead.

Abstract: In a network for transferring a source field in a source word into a destination field in a destination word two basic hardware sub-functions are utilized: rotation and mask vector generation. In the network the destination field of a destination word is masked. Concurrently in the network, a source word is rotated bringing the source field thereof into corresponding alignment with the masked destination field and all but the source field of the source word is masked. Subsequent logical combining of the masked destination word and the rotated and masked source word generates the desired field transference. In one embodiment the required masking operation is accomplished during a single pass of the destination and source words through the network. In an alternate embodiment using less masking hardware only half of the required masking is accomplished during each pass and two passes are required before the logical combining to achieve the desired field transference.