Abstract: Disclosed are various embodiments for integrated diffuse correlation spectroscopy. A first control signal can be sent to a switch to cause an integrator to integrate a current from a photodiode. An integrated current can be received from the integrator, and a data signal can be sent to a computing device based at least in part on the integrated current. A second control signal can be sent to a switch to cause the integrator to cease integrating the current from the photodiode.

Abstract: A system configured to perform the DCS-type measurements with the use of low-coherence continuous-wave (CW) light source at levels of light intensities that are substantially lower and with pathlengths through the tissue that are substantially longer than those afforded by the use of conventional methods. The method includes utilizing the optical detection system to producing signals representing interference between the portion of CW light arriving through reference arm of interferometer and the sample CW light potion that has traversed the sample arm including different paths through the target tissue while switching between first and second of said different paths only by adjusting a delay in the delay line. The spatial resolution of different pathlengths of sample light through tissue is defined by coherence length of CW light.

Abstract: Disclosed are various embodiments for integrated diffuse correlation spectroscopy. A first control signal can be sent to a switch to cause an integrator to integrate a current from a photodiode. An integrated current can be received from the integrator, and a data signal can be sent to a computing device based at least in part on the integrated current. A second control signal can be sent to a switch to cause the integrator to cease integrating the current from the photodiode.

Abstract: Systems or methods for losslessly compressing data received from sensors, such as photon counters, are disclosed. An integer representation of a sensor reading is received from a sensor. The integer representation is combined with additional integer representations from each of a plurality of additional sensors into a single integer value. The single integer value is then stored as an element of an integer array that represents a predefined sample interval.

Abstract: Disclosed are various embodiments for integrated diffuse correlation spectroscopy. A first control signal can be sent to a switch to cause an integrator to integrate a current from a photodiode. An integrated current can be received from the integrator, and a data signal can be sent to a computing device based at least in part on the integrated current. A second control signal can be sent to a switch to cause the integrator to cease integrating the current from the photodiode.

Abstract: Embodiments may relate to a microelectronic package that includes a package substrate with an active bridge positioned therein. An active die may be coupled with the package substrate, and communicatively coupled with the active bridge. A photonic integrated circuit (PIC) may also be coupled with the package substrate and communicatively coupled with the active bridge. Other embodiments may be described or claimed.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for a photonics integrated circuit (IC) for an optical neural network (ONN). In embodiments, the photonics IC includes monolithically optoelectronic components in a single semiconductor substrate including a combination of one or more of integrated array of light sources, a plurality of optical modulators, an optical unitary matrix multiplier, non-linear optical amplifiers or attenuators, and a plurality of photodetectors. In embodiments, the optical unitary matrix multiplier comprises a plurality of 2×2 unitary optical matrices optically interconnected, wherein each 2×2 unitary optical matrix comprises a plurality of phase shifters. In embodiments, each 2×2 unitary optical matrix is to phase shift, split, and/or combine one or more of the optical signal inputs. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for an optical accelerator including a photonics integrated circuit (PIC) for an optical neural network (ONN). In embodiments, an optical accelerator package includes the PIC and an electronics integrated circuit (EIC) that is heterogeneously integrated into the optical accelerator package to proximally provide pre- and post-processing of optical signal inputs and optical signal outputs provided to and received from an optical matrix multiplier of the PIC. In some embodiments, the EIC is a single EIC or discrete EICs to provide pre- and post-processing of the optical signal inputs and optical signal outputs including optical to electrical and electrical to optical transduction. Other embodiments may be described and/or claimed.

Abstract: Embodiments may relate to a segment driver that is to be coupled with a modulator segment of a Mach-Zehnder modulator. The segment driver may include a continuous-time linear equalizer (CTLE) incorporated within an amplifier stage of the modulator. The CTLE may be configured to identify an electrical signal that is related to an optical signal of the Mach-Zehnder modulator; reduce inter-symbol interference (ISI) of the electrical signal to generate a processed electrical signal; and output the processed electrical signal to the amplifier stage. Other embodiments may be described or claimed.

Abstract: Embodiments may relate to a segment driver that is to be coupled with a modulator segment of a Mach-Zehnder modulator. The segment driver may include a continuous-time linear equalizer (CTLE) incorporated within an amplifier stage of the modulator. The CTLE may be configured to identify an electrical signal that is related to an optical signal of the Mach-Zehnder modulator; reduce inter-symbol interference (ISI) of the electrical signal to generate a processed electrical signal; and output the processed electrical signal to the amplifier stage. Other embodiments may be described or claimed.

Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Abstract: A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Abstract: The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667).

Abstract: The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.

Abstract: A system and method is disclosed for computer-assisted transistor design. A new transistor design can be generated based on characteristics of an existing transistor. The system for transistor design receives a first set of parameters for an existing transistor design that are functions of a first geometry that is descriptive of the existing transistor design. Next, the system establishes a set of constraints for the new transistor to be designed. The system then calculates pertinent dimensions of a geometry for the new transistor design based on the constraints and the first set of parameters.

Abstract: The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667).

Abstract: The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.