Abstract: A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide seminconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.

Abstract: A central clock signal generator generates a plurality of odd and even clock pulses which are distributed to a plurality of logic and circuit modules by clock signal lines of equal length. The central signal generator also generates a plurality of gate pulses which are supplied to the modules on signal lines which can be different in length from one to another. The gate pulses are wide enough to coincide with the clock pulses with appropriate allowance for skew between the pulses. For each pair of pulses engaged delivered to a module a detection circuit is provided which detects if the gate pulse and the clock pulse begin and end in the proper sequence. If an improper sequence occurs, the information is stored in a scannable latch and a machine stop control is generated. The exact failing module can be traced readily from the information supplied in this manner.