Abstract: Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log2(Y)) and C=ceiling(log2(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S<Y, the system sets E=S. Otherwise, if S?Y, the system sets E=S?Y.

Abstract: Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

Abstract: A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Each column is stored in a different memory component. When the memory system determines that a memory component has failed, the memory system examines the pattern of errors associated with the failed component to determine if the failure affects a partial component associated with S or fewer bits. If so, the memory system corrects and remaps data bits from the failed partial component to the S spare data bits in the inner-checkbit column.

Abstract: Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.

Abstract: Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

Abstract: A memory system accesses a block of data, each block including bits logically divided into rows and columns, each column including a row-checkbit column, an inner-checkbit column, and data-bit columns. Each column is stored in a different memory component, and checkbits are generated from databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. The system calculates a row syndrome and an inner syndrome for the block of data, the inner syndrome resulting from any two-bit error in the same row being unique. The system can use the row and inner syndromes to determine whether errors are associated with a failed memory component. If not, the system can use the row and inner syndromes, and inner syndromes for all possible combinations of one-bit errors occurring in two rows with a row syndrome of one to correct two bits.

Abstract: Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C?2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed.

Abstract: The disclosed embodiments relate to a memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. During operation, the memory system accesses blocks of data, wherein each block of data includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Moreover, each column is stored in a different memory component, and the checkbits are generated from the data bits to provide guaranteed detection and probabilistic correction for a failed memory component.

Abstract: The disclosed embodiments relate to a memory system that provides guaranteed component-failure correction and double-error correction. During operation, the memory system accesses a block of data, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row checkbits for each of the R rows, (2) an inner-checkbit column containing R inner checkbits, and (3) C-2 data-bit columns containing databits. In addition, each column is stored in a different memory component, and the checkbits are generated from the databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. Next, the system calculates a row syndrome and an inner syndrome for the block of data, wherein the inner syndrome that results from any two-bit error in the same row is unique.

Abstract: Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log2(Y)) and C=ceiling(log2(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S<Y, the system sets E=S. Otherwise, if S?Y, the system sets E=S?Y.

Abstract: Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C-2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed.

Abstract: Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.

Abstract: Methods and apparatuses are presented for reducing the power consumed in an in-line memory module. In some embodiments, the method may include monitoring a memory requirement of a computer system, the computer system comprising a plurality of memory modules. In the event that the memory requirement changes, unmapping at least one of the plurality of memory modules and maintaining a low power state for the at least one unmapped memory module. The method may further comprise selectively re-initializing the plurality of memory modules such that the at least one unmapped memory module remains in a low power state while the remainder of the plurality of memory modules are in a non-low power state. Where, in the event that the memory requirement changes again, the method also may comprise re-programming the memory controller with an identifier associated with the at least one unmapped memory module.

Abstract: A multiple clock domain system. A system comprises two clock domains which receive a source clock signal. The first domain includes a first clock signal with a first frequency and the second domain includes a second clock signal with a second frequency. A ratio of the first frequency to the second frequency is N:M. The first domain is configured to initialize a count to N, if N is less than 2*M; and initialize the count to M, if N is not less than 2*M. Subsequently, on each cycle of the first clock signal, the first domain adds (M-N) to the count and asserts a sample enable signal, if the count is greater than or equal to N; and adds a value equal to M to the count and negates the sample enable signal, if the count is not greater than or equal to N.