Abstract: Fault tolerance is provided in a cross-connect system having only duplicated switch fabrics, instead of the triplicated switch fabrics of the prior art. In addition to the two information switch fabrics, the cross-connect system has a relatively small code switch fabric which switches check-code signals generated at each input interface for each input signal sent to an information switch fabric. Fault-detection and error-recovery components in each output interface (1) generate local check-code signals for each outgoing signals received from an information switch fabric and (2) compare those local check-code signals to the corresponding check-code signal received from the code switch fabric to detect a failure and to select a healthy signal as the output signal for that output interface. In one embodiment, input and output interfaces are clustered, and the corresponding input and output check-code signals are multiplexed, for even greater savings in overhead (e.g.

Abstract: The present co-synthesis technique takes as an input embedded system specification in terms of acyclic task graphs, system constraints, and a resource library consisting of several functional blocks such as processor cores, memory, proprietary and non-proprietary functional blocks, and generates a low-cost hardware and software architecture for systems-on-a-chip such that all real time constraints are met while minimizing average power dissipation. It employs a floor-planning based delay estimator during evaluation of various architectures. Actual delay measurements made on synthesized chips indicate that the delay estimator error is less than 12%. The technique can be extended to derive fault-tolerant architectures for systems-on-a-chip employed in critical applications. Fault-detection capability is imparted to the system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. Error recovery is achieved by switching to spare functional blocks.

Abstract: Error control coding is applied to data streams transmitted through transmission equipment such as a telecommunications switch having a distributed synchronous switch fabric. Each k-symbol dataword is encoded to generate an n-symbol codeword that is then sliced for transmission through the transmission equipment. After routing, error-correction decoding is applied to the resulting routed n-symbol codeword to detect and correct one or more errors in the codeword to generate a k-symbol routed dataword that is identical to the original incoming dataword. Depending on the coding scheme, different types and numbers of errors can be corrected in each codeword. For example, for Reed-Solomon [12, 8, 5] coding with Galois field (24), corrections can be made for up to four erasures with no random errors, up to two erasures and one; random error, or up to two random errors with no erasures.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment, a co-synthesis algorithm, called CRUSADE, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. CRUSADE addresses the co-synthesis of dynamically reconfigurable architectures. Fault-tolerant distributed embedded systems can offer high performance as well as dependability (reliability) and availability to meet the needs of critical real-time applications. The present invention can be easily extended to address the needs of fault-tolerant systems.

Abstract: Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives.

Abstract: Hardware-software co-synthesis is the process of portioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. In the present invention, clusters are selected for allocation during a synthesis phase using both priority levels and costs of communication for the clusters. In another embodiment, a power distribution architecture (PDA) derivation phase, following the synthesis phase, automatically derives a PDA for the embedded system, wherein the PDA defines power supply capacity and interconnection of any necessary power converters to meet power requirements of the embedded system.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.

Abstract: Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead.

Abstract: Hardware-software co-synthesis of an embedded system requires mapping of its specifications into hardware and software modules such that its real-time and other constraints are met. Embedded system specifications are generally represented by acyclic task graphs. Many embedded system applications are characterized by aperiodic as well as periodic task graphs. Aperiodic task graphs can arrive for execution at any time and their resource requirements vary depending on how their constituent tasks and edges are allocated. Traditional approaches based on a fixed architecture coupled with slack stealing and/or on-line determination of how to serve aperiodic task graphs are not suitable for embedded systems with hard real-time constraints, since they cannot guarantee that such constraints would always be met. The present invention addresses the problem of concurrent co-synthesis of aperiodic and periodic specifications of embedded systems.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.

Abstract: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has a pre-processing phase during which task graphs, system/task constraints, and a resource library for the embedded system are parsed, wherein the resource library has different PEs requiring different power supply voltages.