Abstract: A machine learning (ML) model is described herein that predicts computational resource requirements (e.g., a memory and/or runtime metric) for evaluating an integrated circuit (IC) design (e.g., static verification) based on design features extracted from the IC design and auxiliary features related to the IC design. The model may be used to predict the metric for sub-blocks of the IC design. A platform selector may select one of multiple platforms on which to evaluate the IC design or sub-blocks of the IC design based on the predicted metric(s) and specifications of the platforms. The model may be trained to correlate a combination of design features extracted from training IC designs and auxiliary features related to the training IC designs, with metrics of computational resources used in evaluation of the training IC designs, such as with a multiple-linear-regression-based supervised learning technique.

Abstract: A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design with another combined feature array, and reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.

Abstract: The independent claims of this patent signify a concise description of embodiments. An automatic process for determining and/or predicting the original root-cause(s) of a violation is proposed using two major enhancements on top of the current VC-Static solution. First, an information repository is created by mining various Static checker components' analysis information, and second, an analysis framework is created which systematically prunes the above-mentioned information repository to find the actual root cause(s) of the violation. This Abstract is not intended to limit the scope of the claims.

Abstract: A system performs efficient verification of a circuit design. The system receives a circuit design including circuit blocks. The system identifies some of the circuit blocks as modeled circuit blocks. The system generates simplified reduced models (SRMs) for the modeled circuit blocks. A simplified reduced model includes circuit details sufficient for static verification of the circuit design but excludes some of the circuit details for the modeled circuit block. The system performs static verification of the circuit design using the simplified reduced models.

Abstract: Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.

Abstract: A power intent specification specifies the desired power intent for a design of an integrated circuit, for example the states of the power domains under different conditions. Power-aware formal properties describe desired behaviors specified by the power intent specification. Falsified power-aware formal properties indicate that the design does not exhibit the desired behavior. In addition, a debug context database contains debug contexts for static-check violations resulting from power-aware static checking of the design. Static checking checks for compliance with the power intent specification based on a static structure of the design. Falsified power-aware formal properties ae matched against the static-check violations. A data structure is generated, associating debug contexts for the matching static-check violations as possible causes of the falsified power-aware formal properties.

Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

Abstract: A system and method generates cluster-based power architecture interfaces for an integrated circuit (IC) design under test (DUT) debugging by receiving design data for an IC DUT, determining power characteristic data for the IC DUT, generating display components within a graphical user interface (GUI) corresponding to individual components encompassed within a power intent hierarchy corresponding with the IC DUT, generating graphical links between displayed components, overlaying interactive elements corresponding with generated violation clusters over graphical links, and providing root-cause interactive elements within the generated GUI having visual associations with the interactive components corresponding with particular violation clusters.

Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

Abstract: A system and method generates cluster-based power architecture interfaces for an integrated circuit (IC) design under test (DUT) debugging by receiving design data for an IC DUT, determining power characteristic data for the IC DUT, generating display components within a graphical user interface (GUI) corresponding to individual components encompassed within a power intent hierarchy corresponding with the IC DUT, generating graphical links between displayed components, overlaying interactive elements corresponding with generated violation clusters over graphical links, and providing root-cause interactive elements within the generated GUI having visual associations with the interactive components corresponding with particular violation clusters.

Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.

Abstract: Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.

Abstract: The independent claims of this patent signify a concise description of embodiments. An automatic process for determining and/or predicting the original root-cause(s) of a violation is proposed using two major enhancements on top of the current VC-Static solution. First, an information repository is created by mining various Static checker components' analysis information, and second, an analysis framework is created which systematically prunes the above-mentioned information repository to find the actual root cause(s) of the violation. This Abstract is not intended to limit the scope of the claims.

Abstract: Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.

Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.

Abstract: Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.