Abstract: A circuit may perform a skew correction process that positions clock pulses of an output clock signal in respective target sampling positions. The circuit may receive an input clock signal and an input data signal and select one of a plurality of predetermined skew cases for the input clock signal and the input data signal. In addition, the circuit may performing timing relationship measurements for transition permutations of the clock signal and the data signal. The circuit may determine which of the input clock signal and the input data signal to delay and an amount of the delay based on the selected skew case and the timing relationship measurements. An output of the circuit may delay the input clock signal or the input data signal according to the determinations, which centers the sampling transitions of the clock signal in target sampling positions.

Abstract: Electrostatic discharge (ESD) protection for an electronic circuit includes a timer circuit that controls multiple clamp circuits. In this way, less circuit area may be used for the timer circuit as compared to conventional ESD protection schemes. In some embodiments, the ESD protection circuit is employed in a data storage apparatus that includes a non-volatile memory array (e.g., NAND devices).

Abstract: The disclosure relates in some aspects to electrostatic discharge (ESD) protection for an electronic circuit. In some aspects, the ESD protection includes a timer circuit that controls multiple clamp circuits. In this way, less circuit area may be used for the timer circuit as compared to conventional ESD protection schemes. In some embodiments, the ESD protection circuit is employed in a data storage apparatus that includes a non-volatile memory array (e.g., NAND devices).

Abstract: A circuit may perform a skew correction process that positions clock pulses of an output clock signal in respective target sampling positions. The circuit may receive an input clock signal and an input data signal and select one of a plurality of predetermined skew cases for the input clock signal and the input data signal. In addition, the circuit may performing timing relationship measurements for transition permutations of the clock signal and the data signal. The circuit may determine which of the input clock signal and the input data signal to delay and an amount of the delay based on the selected skew case and the timing relationship measurements. An output of the circuit may delay the input clock signal or the input data signal according to the determinations, which centers the sampling transitions of the clock signal in target sampling positions.

Abstract: A circuit may include control circuitry configured to determine a duty cycle error for a sample clock signal. Based on the duty cycle error the control circuitry may determine a corrective direction by which to alter the duty cycle to correct the duty cycle error. The control circuitry may indicate the corrective direction to selection circuitry via a selection signal. Responsive to the selection signal, the selection circuitry may select a leading phase signal and a lagging phase signal from among a plurality of relative phase signals. Output circuitry may combine the leading phase signal and a lagging phase signal to generate an output clock signal with a duty cycle corresponding the corrective direction.

Abstract: Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Abstract: Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Abstract: A DLL circuit includes a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, a first controller for setting the bias current, and a second controller for selecting an output-producing variable delay element from the plural its of the variable delay elements.

Abstract: There is provided a DLL circuit that uses a small amount of area on a chip, and is compatible with a wide range of clock frequencies. The DLL circuit has a delay line 210 for delaying an external clock signal CLK, and a control circuit for controlling a delay value by using the delay line 210. The delay line 210 has a plurality of cascade connected variable delay elements 500. The variable delay elements 500 have a differential circuit structure for varying the delay value by using a bias current. The control circuit has a first controller 300 for setting the bias current, and a second controller 400 for selecting an output-producing variable delay element from among the plurality of variable delay elements 500. According to the present invention, it is possible to handle a wide variety of clock frequencies by using a low number of stages, since the delay line is configured from variable delay elements.