Patents by Inventor Bheom S. Joo

Bheom S. Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5594762
    Abstract: This invention relates to an apparatus for retiming digital data transmitted at a high speed even though the phase of a binary data bit is not related to the phase of the static offset of a retiming clock pulse, the apparatus comprising: local clock pulse generation means 11 for generating and outputting local clock pulse FT; delayed clock pulse parallel generation means 12 for outputting, in parallel, n delayed clock pulses delayed sequentially by one cycle of local clock pulse FT; input data transition detection means 13 for outputting pulse DT each time the rising and falling carrier waves intersect in input data D; sequential logic parallel phase detection means 14 for providing clock pulse selection data by outputting sequential logic phases of the upper location of the pulse generated during input data transition and transition location of n delayed clock pulses; retiming clock pulse selection means 15 for outputting a retiming clock pulse according to the clock pulse selection data of the input delayed
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: January 14, 1997
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Bheom S. Joo, Bhum C. Lee, Jung S. Kim, Seok Y. Kang
  • Patent number: 5525935
    Abstract: A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass f
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: June 11, 1996
    Assignees: Electronics and Telecommunications Research Institute, Korea Telecommunications Authority
    Inventors: Bheom S. Joo, Bheom C. Lee, Kwon C. Park, Seok Y. Kang