Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

Abstract: An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

Abstract: An apparatus for biasing a plurality of microphones includes a sensing circuit that actively senses a local ground reference for each microphone. An intermediate stage receives a constant non-local reference voltage as an input and responsively provides a respective constant local reference signal (e.g., current) with respect to each of the actively sensed local ground references. For each microphone, a respective microphone bias block uses the respective constant local reference signal to generate a respective constant local microphone bias voltage to bias the microphone. For each microphone, a variable RC network uses the respective constant local reference current to generate a constant local reference voltage for the microphone. Each RC network is controllable in response to the respective actively sensed local ground reference to independently set the respective local microphone bias voltage.

Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

Abstract: An apparatus for biasing a plurality of microphones includes a sensing circuit that actively senses a local ground reference for each microphone. An intermediate stage receives a constant non-local reference voltage as an input and responsively provides a respective constant local reference signal (e.g., current) with respect to each of the actively sensed local ground references. For each microphone, a respective microphone bias block uses the respective constant local reference signal to generate a respective constant local microphone bias voltage to bias the microphone. For each microphone, a variable RC network uses the respective constant local reference current to generate a constant local reference voltage for the microphone. Each RC network is controllable in response to the respective actively sensed local ground reference to independently set the respective local microphone bias voltage.

Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract: In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.

Abstract: In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.

Abstract: A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

Abstract: A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

Abstract: A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.