Abstract: A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance is divided by sum of the ground capacitance and the coupling capacitance to compute a scale factor. The effective capacitance is then scaled by the scale factor to determine a delay noise induced load. Finally, the timing paths are optimized incrementally by using the delay noise induced load, the resistance, and the delay information.

Abstract: The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability.