Patents by Inventor Bi-Ling Lin
Bi-Ling Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901289Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.Type: GrantFiled: June 23, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
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Publication number: 20220319987Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.Type: ApplicationFiled: June 23, 2022Publication date: October 6, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
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Patent number: 11404369Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: GrantFiled: May 24, 2019Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
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Patent number: 10978440Abstract: A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.Type: GrantFiled: August 7, 2019Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shou-En Liu, Chun-Wei Chang, Bi-Ling Lin, Yung-Sheng Tsai, Jiaw-Ren Shih
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Publication number: 20190363075Abstract: A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Inventors: Shou-En LIU, Chun-Wei CHANG, Bi-Ling LIN, Yung-Sheng TSAI, Jiaw-Ren SHIH
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Publication number: 20190279933Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
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Patent number: 10403621Abstract: A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.Type: GrantFiled: October 29, 2014Date of Patent: September 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shou-En Liu, Chun-Wei Chang, Bi-Ling Lin, Yung-Sheng Tsai, Jiaw-Ren Shih
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Patent number: 10304772Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: GrantFiled: May 19, 2017Date of Patent: May 28, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
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Publication number: 20180337125Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
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Patent number: 9875964Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: GrantFiled: January 28, 2014Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Publication number: 20160126232Abstract: A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Shou-En LIU, Chun-Wei CHANG, Bi-Ling LIN, Yung-Sheng TSAI, Jiaw-Ren SHIH
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Patent number: 8848374Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.Type: GrantFiled: June 30, 2010Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hong Lin, Chin Chuan Peng, Tzu-Li Lee, Bi-Ling Lin, Bor-Jou Wei, Chien Shih Tsai
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Publication number: 20140145194Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: ApplicationFiled: January 28, 2014Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Patent number: 8648592Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: GrantFiled: September 13, 2011Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Publication number: 20130063175Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Publication number: 20120002375Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hong LIN, Chin Chuan PENG, Tzu-Li LEE, Bi-Ling LIN, Bor-Jou WEI, Chien Shih TSAI
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Patent number: 7646207Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.Type: GrantFiled: September 4, 2007Date of Patent: January 12, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
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Publication number: 20090058434Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.Type: ApplicationFiled: September 4, 2007Publication date: March 5, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
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Patent number: 6548363Abstract: A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode.Type: GrantFiled: April 11, 2000Date of Patent: April 15, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Cheng Wu, Bi-Ling Lin, Carlos Hernando Diaz
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Patent number: 6284579Abstract: A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.Type: GrantFiled: October 14, 1999Date of Patent: September 4, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jyh-Haur Wang, Bi-Ling Lin, Chung-Cheng Wu, Carlos H. Diaz