Abstract: A decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. The decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.

Abstract: A decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. The decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.

Abstract: Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.

Abstract: Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.

Abstract: Disclosed herein are an apparatus and method for receiving a signal based on FTN. The apparatus for receiving a signal based on FTN includes an equalizer for creating a Log Likelihood Ratio (LLR) sequence by equalizing an FTN signal sequence sampled at an FTN signaling rate; a deinterleaver for deinterleaving the created LLR sequence; a decoder for decoding the LLR sequence by correcting errors in the deinterleaved LLR sequence; an interleaver for interleaving the decoded LLR sequence and providing the interleaved LLR sequence to the equalizer; and an FTN interference estimation unit for providing the FTN signal sequence, from which an FTN interference sequence is eliminated, to the equalizer, using the interleaved LLR sequence.

Abstract: Disclosed herein are an apparatus and method for receiving a signal based on FTN. The apparatus for receiving a signal based on FTN includes an equalizer for creating a Log Likelihood Ratio (LLR) sequence by equalizing an FTN signal sequence sampled at an FTN signaling rate; a deinterleaver for deinterleaving the created LLR sequence; a decoder for decoding the LLR sequence by correcting errors in the deinterleaved LLR sequence; an interleaver for interleaving the decoded LLR sequence and providing the interleaved LLR sequence to the equalizer; and an FTN interference estimation unit for providing the FTN signal sequence, from which an FTN interference sequence is eliminated, to the equalizer, using the interleaved LLR sequence.

Abstract: A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

Abstract: A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Abstract: An apparatus and method for processing optical information using a low density parity check code are suggested. An optical information recording method includes the steps of encoding data to record into a low density parity check code; representing the data, which is encoded into the low density parity check code, to a spatial light modulator in the unit of a data page; and modulating a recording beam into the data page representing the spatial light modulator to be recorded in the form of hologram in a recording medium. By blocking inexact probability information from being concentrated in the LDPC code block, by achieving exact probability information through effective allocation of a mark, and by improving average accuracy of the pixel, which corresponds to the LDPC code, failure rate of decoding can be minimized so that decoding performance can be improved.

Abstract: A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

Abstract: A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

Abstract: An apparatus and method for processing optical information using a low density parity check code are suggested. An optical information recording method includes the steps of encoding data to record into a low density parity check code; representing the data, which is encoded into the low density parity check code, to a spatial light modulator in the unit of a data page; and modulating a recording beam into the data page representing the spatial light modulator to be recorded in the form of hologram in a recording medium. By blocking inexact probability information from being concentrated in the LDPC code block, by achieving exact probability information through effective allocation of a mark, and by improving average accuracy of the pixel, which corresponds to the LDPC code, failure rate of decoding can be minimized so that decoding performance can be improved.

Abstract: A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.

Abstract: A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.

Abstract: A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.