Patents by Inventor Biagio Gallo

Biagio Gallo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060263540
    Abstract: A method of processing a workpiece includes introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and exposing the workpiece to optical radiation that is at least partially absorbed in the optical absorber layer.
    Type: Application
    Filed: May 17, 2005
    Publication date: November 23, 2006
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash Mayur, Amir Al-Bayati, Andrew Nguyen
  • Publication number: 20060260545
    Abstract: An integrated system for processing a semiconductor wafer includes a toroidal source plasma reactor for depositing a heat absorbing layer, the reactor including a wafer support, a reactor chamber, an external reentrant toroidal conduit coupled to said chamber on generally opposing sides thereof, an RF source power applicator for coupling power to a section of said external reentrant conduit and a process gas source containing a heat absorbing material precursor gas. The integrated system further includes an optical annealing chamber.
    Type: Application
    Filed: May 17, 2005
    Publication date: November 23, 2006
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash Mayur, Amir Al-Bayati, Andrew Nguyen
  • Publication number: 20060264060
    Abstract: A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and coupling RF plasma bias power or bias voltage to the workpiece.
    Type: Application
    Filed: May 17, 2005
    Publication date: November 23, 2006
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash Mayur, Amir Al-Bayati, Andrew Nguyen
  • Patent number: 7137354
    Abstract: A plasma immersion ion implantation reactor for ion implanting a species into a surface layer of a workpiece includes an enclosure which has a side wall and a ceiling defining a chamber and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceiling and defining a process region extending generally across the wafer support pedestal and confined laterally by the side wall and axially between the workpiece support pedestal and the ceiling. The enclosure has at least a first pair of openings at generally opposite sides of the process region and a first hollow conduit outside of the chamber having first and second ends connected to respective ones of the first pair of openings, so as to provide a first reentrant path extending through the conduit and across said process region.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: November 21, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo, Gonzalo Antonio Monroy
  • Publication number: 20060237136
    Abstract: A valve system having high maximum gas flow rate and fine control of gas flow rate, includes a valve housing for blocking gas flow through a gas flow path, a large area opening through said housing having a first arcuate side wall and a small area opening through said housing having a second arcuate side wall, and respective large area and small area rotatable valve flaps in said large area and small area openings, respectively, and having arcuate edges congruent with said first and second arcuate side walls, respectively and defining therebetween respective first and second valve gaps. The first and second valve gaps are sufficiently small to block flow of a gas on one side of said valve housing up to a predetermined pressure limit, thereby obviating any need for O-rings.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 26, 2006
    Inventors: Andrew Nguyen, Hiroji Hanawa, Kenneth Collins, Kartik Ramaswamy, Amir Al-Bayati, Biagio Gallo
  • Publication number: 20060238953
    Abstract: A lift pin assembly for use in a reactor for processing a workpiece includes plural lift pins extending generally parallel with a lift direction, each of the plural lift pins having a top end for supporting a workpiece and a bottom end. A lift table faces the bottom ends of the pins and is translatable in a direction generally parallel with the lift direction. A small force detector senses a force exerted by the lift pins that is sufficiently large to indicate a chucked wafer and sufficiently small to avoid dechucking a wafer A large force detector senses a force exerted by the lift pins in a range sufficient to de-chuck the wafer.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 26, 2006
    Inventors: Hiroji Hanawa, Andrew Nguyen, Kenneth Collins, Kartik Ramaswamy, Biagio Gallo, Amir Al-Bayati
  • Patent number: 7109098
    Abstract: A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and optically annealing the workpiece so as to activate dopant impurities in the semiconductor material.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: September 19, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Patent number: 7094670
    Abstract: A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma while minimizing deposition and minimizing etching by holding the temperature of the workpiece within a temperature range that is above a workpiece deposition threshold temperature and below a workpiece etch threshold temperature.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: August 22, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Patent number: 7037813
    Abstract: A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpiece and the ceiling, and introducing into the chamber a process gas including the species to be implanted in the surface layer of the workpiece. The method includes generating from the process gas a plasma by capacitively coupling RF source power across the workpiece support and the ceiling or the sidewall from an RF source power generator. The method further includes applying an RF bias from an RF bias generator to the workpiece support.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: May 2, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo, Gonzalo Antonio Monroy
  • Publication number: 20060088655
    Abstract: A method of measuring ion dose in a plasma immersion ion implantation reactor during ion implantation of a selected species into a workpiece includes placing the workpiece on a pedestal in the reactor and feeding into the reactor a process gas comprising a species to be implanted into the workpiece, and then coupling RF plasma source power to a plasma in the reactor. It further includes coupling RF bias power to the workpiece by an RF bias power generator that is coupled to the workpiece through a bias feedpoint of the reactor and measuring RF current at the feedpoint to generate a current-related value, and then integrating the current-related over time to produce an ion implantation dose-related value.
    Type: Application
    Filed: October 23, 2004
    Publication date: April 27, 2006
    Inventors: Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Amir Al-Bayati, Andrew Nguyen, Biagio Gallo
  • Publication number: 20060081558
    Abstract: A method of processing a workpiece includes placing the workpiece on a workpiece support pedestal in a main chamber with a gas distribution showerhead, introducing a process gas into a remote plasma source chamber and generating a plasma in the remote plasma source chamber, transporting plasma-generated species from the remote plasma source chamber to the gas distribution showerhead so as to distribute the plasma-generated species into the main chamber through the gas distribution showerhead, and applying plasma RF power into the main chamber.
    Type: Application
    Filed: January 28, 2005
    Publication date: April 20, 2006
    Inventors: Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Publication number: 20060073683
    Abstract: A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking voltage to the electrostatic chuck. The method further includes introducing into the chamber a precursor gas including a species to be ion implanted in the workpiece and applying an RF bias to the electrostatic chuck, the RF bias having a bias level corresponding to the ion implantation profile depth.
    Type: Application
    Filed: November 21, 2005
    Publication date: April 6, 2006
    Inventors: Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo, Gonzalo Monroy
  • Patent number: 6965116
    Abstract: Dose uniformity of a scanning ion implanter is determined. A base beam current is measured at the beginning and/or the end of a complete scan over the whole substrate area. This base beam current is measured at a time when the measurement should be unaffected by outgassing from a substrate being implanted and a base dose distribution map is then calculated for the scan in question. During the scan itself beam instability events are detected and the magnitude and position in the scan of the detected instability events is measured. Corresponding deviations in the calculated base dose map are determined and subtracted from the previously calculated base dose distribution map to provide a corrected distribution map. By determining overall dose uniformity substractively in this way, good overall accuracy can be obtained with lesser accuracy in the measurement of the beam instability events.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: November 15, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Dennis W. Wagner, Biagio Gallo, Peter Torin Kindersley, David Eugene Aberle, Jonathon Yancey Simmons
  • Publication number: 20050230047
    Abstract: A plasma reactor for performing plasma immersion ion implantation, dopant deposition or surface material enhancement, includes a vacuum chamber, a wafer support pedestal or electrostatic chuck having an insulated electrode underlying a wafer support surface within said chamber, a chucking voltage source coupled to the insulated electrode, a thermal sink coupled to the electrostatic chuck, an RF bias power generator coupled to said electrostatic chuck, and a process gas supply and gas inlet ports coupled to the chamber and coupled to the gas supply. The process gas supply contains either (a) a gas containing a dopant species to be ion implanted in a semiconductive material of workpiece, (b) a gas containing a dopant species to be deposited on a surface of a semiconductive material of a workpiece, or (c) a gas containing a material enhancement species to be ion implanted into a workpiece.
    Type: Application
    Filed: January 28, 2005
    Publication date: October 20, 2005
    Inventors: Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Publication number: 20050191830
    Abstract: A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level; performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma while minimizing deposition and minimizing etching by holding the temperature of the workpiece within a temperature range that is above a workpiece deposition threshold temperature and below a workpiece etch threshold temperature.
    Type: Application
    Filed: January 28, 2005
    Publication date: September 1, 2005
    Inventors: Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Publication number: 20050191827
    Abstract: One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning film precursor gas into the chamber and generating a plasma within the chamber, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma, and then removing the workpiece from the chamber and removing the seasoning film from the chamber interior surfaces.
    Type: Application
    Filed: January 28, 2005
    Publication date: September 1, 2005
    Inventors: Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Publication number: 20050191828
    Abstract: An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.
    Type: Application
    Filed: December 1, 2004
    Publication date: September 1, 2005
    Inventors: Amir Al-Bayati, Rick Roberts, Kenneth Collins, Ken MacWilliams, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen
  • Publication number: 20050136604
    Abstract: A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.
    Type: Application
    Filed: December 1, 2004
    Publication date: June 23, 2005
    Inventors: Amir Al-Bayati, Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen
  • Patent number: 6893907
    Abstract: A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: May 17, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Dan Maydan, Randir P. S. Thakur, Kenneth S. Collins, Amir Al-Bayati, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen
  • Publication number: 20050070073
    Abstract: A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of the pair of wafers. The method further includes performing a cleavage ion implantation step on one of the pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of the wafer at the predetermined depth below the top surface of the one wafer. The wafers are then bonded together by placing the first surfaces of the pair of wafers onto one another so as to form an semiconductor-on-insulator structure.
    Type: Application
    Filed: November 16, 2004
    Publication date: March 31, 2005
    Inventors: Amir Al-Bayati, Kenneth Collins, Hiroji Hanawa, Kartik Ramaswamy, Biagio Gallo, Andrew Nguyen