Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.

Abstract: An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract: In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.

Abstract: A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer.

Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Abstract: An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.