Patents by Inventor BIJIAN CHEN

BIJIAN CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11526651
    Abstract: Embodiments of the invention include protecting against antenna violations in a macro having a clock mesh. Aspects include obtaining a design of the macro, the design including a clock layer having a plurality of clock pins and determining a longest vertical wire and a longest horizontal wire allowed based on a design of the clock mesh. Aspects also include identifying, based at least in part on the longest vertical wire and the longest horizontal wire, a plurality of checkbox regions for a clock pin of the plurality of clock pins and calculating a total diffusion area for each of the plurality of checkbox regions. Aspects further include adding, to the design of the macro, an antenna diode to the clock pin based on a determination that the total diffusion area for any of the plurality of checkbox regions is less than a threshold value.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: December 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Amanda Christine Venton, Bijian Chen, Eric Chien Lai, Peter Milton Nasveschuk
  • Publication number: 20200380082
    Abstract: A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Stephen Thomas Quay, Yaoguang Wei, Bijian Chen, Ying Zhou
  • Patent number: 10839122
    Abstract: A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen Thomas Quay, Yaoguang Wei, Bijian Chen, Ying Zhou
  • Patent number: 10831971
    Abstract: Methods and systems for improving the performance of a computer performing an electronic design. One or more nets of a netlist are sorted based on an amount of slack and a net of the one or more nets that is unprocessed and that has a least amount of slack is selected as a current target net. A layer of a higher bucket that is unprocessed for the currently selected target net is selected, the higher bucket being higher than a bucket of the current target net. A determination of whether capacity is available to route the current target net on the selected layer of the higher bucket is made and the current target net is routed on the selected layer of the higher bucket in response to capacity being available. One or more nets that are competing for resources with the current target net on the selected layer of the higher bucket are identified as candidate nets in response to capacity not being available.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen Thomas Quay, Yaoguang Wei, Bijian Chen, Ying Zhou
  • Publication number: 20190203816
    Abstract: A continuously variable transmission steering mechanism of a tracked vehicle, comprising a differential (1), a right drive shaft (2), a left drive shaft (3), and a continuously variable transmission (4) used for adjusting the rotational speed of the right drive shaft (2) and that of the left drive shaft (3). A left half shaft (5) and a right half shaft (6) are connected on the differential (1). The right half shaft (6) of the differential (1) is linked to the right drive shaft (2). The right drive shaft (2) rotates to drive the right half shaft (6) of the differential (1) to rotate. The left half shaft (5) of the differential (1) is linked to the left drive shaft (3). The left drive shaft (3) rotates to drive the left half shaft (5) of the differential (1) to rotate. The rotational speed ratio of the right half shaft (6) of the differential (1) to the right drive shaft (2) is equal to the rotational speed ratio of the left half shaft (5) of the differential (1) to the left drive shaft (6).
    Type: Application
    Filed: June 27, 2017
    Publication date: July 4, 2019
    Inventors: Jiangbiao FU, Fulin LIU, Bijian CHEN
  • Patent number: 9639654
    Abstract: Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: May 2, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bijian Chen, David J. Hathaway, Nathaniel D. Hieter, Kerim Kalafala, Jeffrey S. Piaget, Alexander J. Suess
  • Publication number: 20160171147
    Abstract: Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: BIJIAN CHEN, DAVID J. HATHAWAY, NATHANIEL D. HIETER, KERIM KALAFALA, JEFFREY S. PIAGET, ALEXANDER J. SUESS