Abstract: A circuit for the analog correlation of a signal to remove impairments such as echo, cross talk and intersymbol interference is described. A duplexing circuit which improves echo response by providing a second transformer is described.

Abstract: According to an embodiment of present invention, an algorithm for computing static pre-equalizer coefficients, comprises the steps of determining a length of algorithm iterations; calculating a feedforward coefficient vector associated with a feedforward equalizer; calculating a pre-equalizer coefficient vector associated with a pre-equalizer filter; and performing the steps of calculating for the length of the algorithm iterations; wherein a mean square of an error between an output sequence and a transmitted digital input sequence is minimized.

Abstract: A high-speed broadband, wireline modem including an adaptive equalizer having both a training mode and a decision-directed non-training mode. The adaptive equalizer comprising at least one of a forward path coupled to receive signal samples, the forward path including a forward filter and a decision element, and a feedback path coupled between an output of the decision element and an input of the decision element, the feedback path including a feedback filter; and means for adapting the one of said forward filter and said feedback filter based on a least squares error criterion performed substantially according to a predetermined algorithm.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: The present invention, generally speaking, provides efficient multi-rate trellis encoder and decoder structures. The trellis encoder allows for a variable number of uncoded bits to be represented in a transmit symbol. The decoder maps received symbols to a smaller constellation by dropping selected symbol bits, whereby, for each of multiple cosets, points within that coset are mapped to a fewer number of points. Substantial simplification of the decoder structure is therefore achieved.

Abstract: The present invention comprises a method of obtaining coefficients for a transmit filter such that the power spectral density of the output for the different frequencies comes close to but does not exceed a maximum power spectral density of a communication(s) standard. By first doing a convex optimization procedure to obtain the autocorrelation coefficients for the filter and then using the autocorrelation coefficients to determine the filter coefficients, a low-order filter that closely approximates the desired output power spectral densities can be produced.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: According to an embodiment of present invention, an algorithm for computing static pre-equalizer coefficients, comprises the steps of determining a length of algorithm iterations; calculating a feedforward coefficient vector associated with a feedforward equalizer; calculating a pre-equalizer coefficient vector associated with a pre-equalizer filter; and performing the steps of calculating for the length of the algorithm iterations; wherein a mean square of an error between an output sequence and a transmitted digital input sequence is minimized.

Abstract: An embodiment of the present invention is directed to a rate enhanced system for supporting duplex transmission of symmetric data rates. The system comprises an encoder comprising a serial to parallel converter for receiving a serial data bit, and for generating a parallel word having M bits; a convolutional encoder for receiving a first bit of the M bits of the parallel word, and for generating two encoded bits; and a mapper for receiving the two encoded bits and the remaining M−1 bits of the parallel word, and for generating a symbol; wherein M is greater than three.

Abstract: A dual rate echo canceller for simultaneous support of multiple annexes is provided. The present invention provides an efficient Reduced Complexity Dual Rate Echo Chancellor (RCDR-EC) architecture for ADSL CPE for simultaneous support of a plurality of annexes, such as Annex A and Annex B of G.992.1. In addition, low complexity LMS update rules are proposed for adaptive training RCDR-EC. In addition, RCDR-EC of the present invention may operate at the transmit rate, the lower of the two rates, thereby requiring less computation per data sample. The present invention provides an echo canceller structure for full rate ADSL CPE. Another aspect of the present invention is directed to designing the echo canceller flexible enough to simultaneously support, at least, Annex A and Annex B of G.992.1. Another aspect of the present invention is further directed to obtaining an efficient rate matching echo canceller implementation for full rate ADSL CPE as well as other applications.

Abstract: A minimum mean square error linearly constrained fast algorithm for adaptive training of a Time Domain Equalizer (MLC-TEQ) is provided. A fast adaptive algorithm of the present invention may be used to obtain Finite Impulse Response (FIR) filter coefficients for Time domain Equalizer (TEQ) used in Discrete Multitone (DMT) based applications, such as ADSL, for example. The TEQ coefficients obtained by the algorithm of the present invention shortens the overall effective discrete time channel impulse response length within a given target length (e.g., symbol prefix length for DMT application). Advantages of the proposed data aided adaptive algorithm may include providing the TEQ filter coefficients with near-optimal performance; having low computational requirements, having fast convergence, and exhibiting attractive stability properties. Other advantages may also be realized by the present invention and variations thereof.

Abstract: A weighted error echo canceller for transceivers with unequal bandwidths is provided. The present invention enables an adaptive echo cancellation filter to perform at a lower sample rate. An efficient echo cancellation scheme, referred to as Weighted Vector Error Echo Canceller (WEVE-EC) is proposed for various applications, such as applications where the receive path has a higher sampling rate. The WEVE-EC architecture may be implemented along with an adaptive algorithm, which may be based on Least Mean Square (LMS) update rules. Various other adaptive algorithms may be used to train the WEVE-EC of the present invention. An Error Weighting Multi-input-multi-output Filter (EWMF) of the present invention provides a flexible weighting scheme on most or all the sampling phases of the error signal.

Abstract: A dual rate echo canceller is provided for applications with asymmetric transmit and receive rates. In particular, the present invention provides Reduced Complexity Dual Rate Echo Canceller (RCDR-EC) architecture along with low complexity Least Mean Square (LMS) update rules. According to one aspect, the present invention is directed to an echo canceller that provides rate matching functionality for applications (e.g., ADSL, VDSL, etc.) with asymmetric data rates. The RCDR-EC of the present invention operates at the lower of the two rates, receive and transmit, requiring less computation per data sample. RCDR-EC implements a significantly smaller length echo cancellation filter (ECF) for achieving the same (or similar) level of echo suppression of conventional implementations. This reduces the hardware requirement for implementation of RCDR-EC.

Abstract: The present invention comprises a method of obtaining coefficients for a transmit filter such that the power spectral density of the output for the different frequencies comes close to but does not exceed a maximum power spectral density of a communication(s) standard. By first doing a convex optimization procedure to obtain the autocorrelation coefficients for the filter and then using the autocorrelation coefficients to determine the filter coefficients, a low-order filter that closely approximates the desired output power spectral densities can be produced.

Abstract: A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.