Patents by Inventor Bijoyraj Sahu

Bijoyraj Sahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197622
    Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Karumbu Meyyappan, Jeffory L, Smalley, Gregorio Murtagian, Srikant Nekkanty, Pooya Tadayon, Eric J.M. Moret, Bijoyraj Sahu
  • Publication number: 20220415742
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, and a die, electrically coupled to the package substrate, including a silicon substrate having a first surface and an opposing second surface; a device layer at the first surface of the silicon substrate; and a dielectric layer, having a heater trace, at the second surface of the silicon substrate.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Bijoyraj Sahu, Tolga Acikalin, Anand Haridass, Vikrant Thigle
  • Patent number: 11387163
    Abstract: A microprocessor heat sink fastener, comprising a nut comprising a thermoplastic material and fibrous fill particles and a bore extending along an axis of the nut. The bore has internal threads. The internal threads comprise a surface. At least one of the fibrous fill particles has first and second ends extending from the surface into a sub-surface region.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Andrew Larson, Bijoyraj Sahu, Craig J. Jahne, Eric W. Buddrius, Ralph V. Miele
  • Publication number: 20220196507
    Abstract: An apparatus is described. The apparatus includes a cover to enclose a junction between respective ends of first and second fluidic conduits. The first and second fluidic conduits transport a coolant fluid within an electronic system. The apparatus also includes a leak detection device to be located within a region that is enclosed by the cover when the junction is enclosed by the cover. The leak detection device is to detect a leak of the coolant fluid at the junction when the junction is enclosed by the cover. The first and second fluidic conduits extend outside the cover when the junction is enclosed by the cover. Another apparatus is also described. The other apparatus includes a leak detection device to detect a leak of coolant fluid from a specific component or junction in a liquid cooling system of an electronic system.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Prabhakar SUBRAHMANYAM, Yi XIA, Ying-Feng PANG, Victor POLYANKO, Mark BIANCO, Bijoyraj SAHU, Minh T.D. LE, Carlos ALVIZO FLORES, Javier AVALOS GARCIA, Adriana LOPEZ INIGUEZ, Luz Karine SANDOVAL GRANADOS, Michael BERKTOLD, Damion SEARLS, Jin YANG, David SHIA, Samer MELHEM, Jeffrey Ryan CONNER, Hemant DESAI, John RAATZ, Richard DISCHLER, Bergen ANDERSON, Eric W. BUDDRIUS, Kenan ARIK, Barrett M. FANEUF, Lianchang DU, Yuehong FAN, Shengzhen ZHANG, Yuyang XIA, Jun ZHANG, Yuan Li, Catharina BIBER, Kristin L. WELDON, Brendan T. PAVELEK
  • Patent number: 11291115
    Abstract: A microprocessor carrier, comprising a frame comprising a metal. The first frame surrounds an aperture for receiving a microprocessor package. At least one hinge assembly is on a first frame edge, and at least one latch assembly is on a second frame edge. One or more alignment tabs coupled to the frame. The one or more alignment tabs extend orthogonally from at least one frame edge. The alignment tabs are to align the microprocessor package with a microprocessor socket. The hinge assembly and the latch assembly are to engage with a microprocessor loading mechanism coupled to a printed circuit board.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Shelby A. Ferguson, Bijoyraj Sahu, Russell Aoki, Thomas Boyd, Eric W. Buddrius, Kevin Ceurter, Mustafa Haswarey, Rolf Laido, Daniel Neumann, Rachel Taylor, Anthony Valpiani
  • Publication number: 20210321526
    Abstract: Techniques for liquid cooling systems are disclosed. In one embodiment, a hermetically sealed container includes an integrated circuit component and a two-phase coolant. As the integrated circuit component generates heat, the coolant boils, rising to a lid of the container. A cold plate mated with the lid absorbs heat from the lid, causing condensation of the coolant on the underside of the lid. The coolant then drips back down towards the integrated circuit component. Other embodiments are disclosed.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Devdatta Prakash Kulkarni, Maria De La Luz Belmont Velazquez, Andres Ramirez Macias, Sandeep Ahuja, Tejas Shah, Bijoyraj Sahu
  • Publication number: 20210208647
    Abstract: A processor unit module comprises an integrated circuit component attached to a top side of a printed circuit board and one or more electronic components (e.g., voltage regulator FETs, inductors) attached to a bottom side of the board. The printed circuit board is located between a top stiffener plate and a bottom stiffener frame and the three components are secured together by fasteners that connect the top stiffener plate to the bottom stiffener frame. Flexible thermal straps connect the top stiffener plate to one or more slugs located between the printed circuit board and the bottom stiffener frame. The slugs touch the bottom side of the board and are held in place by the bottom stiffener frame. Heat generated by the bottom side components is transported by the slugs and the thermal straps to a thermal management solution (e.g., heat sink, cold plate) attached to the top side of the module.
    Type: Application
    Filed: February 26, 2021
    Publication date: July 8, 2021
    Applicant: Intel Corporation
    Inventors: Andres Ramirez Macias, Aardra B. Athalye, Devdatta Prakash Kulkarni, Gilberto Rayas Paredes, Bijoyraj Sahu
  • Patent number: 11032941
    Abstract: Systems, apparatuses, methods, and computer-readable media are presented for managing an apparatus for thermal energy management including a first container. The first container includes a first cavity, and is configured to hold a first liquid coolant within the first cavity to at least partially surround a second container. The second container includes a second cavity configured to hold one or more heat sources, and a second liquid coolant to at least partially surround the one or more heat sources. The second container is sealed to separate the first liquid coolant from the second liquid coolant. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Minh Le, Thomas Boyd, Bijoyraj Sahu, Evan Chenelly, Christopher Wade Ackerman, Carlos Alvizo Flores, Craig Jahne
  • Publication number: 20210108860
    Abstract: A variable conductance heat pipe (VCHP) is utilized as a “passive heat switch” to regulate a characteristic temperature of an integrated circuit component. The VCHP is located between an integrated circuit component and a cold plate and comprises a working fluid and a non-condensable gas in a chamber. When the component is not operational, the VCHP blocks the flow of heat from the component to the cold plate. As component power consumption increases, the working fluid pressure increases and compresses the non-condensable gas toward the cooler region of the cold plate to eventually create a low thermal resistance path between the component and the cold plate. By introducing negative feedback into the thermal management solution, the VCHP keeps the characteristic temperature within a narrow range. This can alleviate stress on package components (e.g., solder joints) due to excessive thermal cycling, which can extend the lifetime of the component.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Devdatta Prakash Kulkarni, Bijoyraj Sahu
  • Publication number: 20190304869
    Abstract: A microprocessor heat sink fastener, comprising a nut comprising a thermoplastic material and fibrous fill particles and a bore extending along an axis of the nut. The bore has internal threads. The internal threads comprise a surface. At least one of the fibrous fill particles has first and second ends extending from the surface into a sub-surface region.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Andrew Larson, Bijoyraj Sahu, Craig J. Jahne, Eric W. Buddrius, Ralph V. Miele
  • Publication number: 20190306985
    Abstract: A microprocessor carrier, comprising a frame comprising a metal. The first frame surrounds an aperture for receiving a microprocessor package. At least one hinge assembly is on a first frame edge, and at least one latch assembly is on a second frame edge. One or more alignment tabs coupled to the frame. The one or more alignment tabs extend orthogonally from at least one frame edge. The alignment tabs are to align the microprocessor package with a microprocessor socket. The hinge assembly and the latch assembly are to engage with a microprocessor loading mechanism coupled to a printed circuit board.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Shelby A. Ferguson, Bijoyraj Sahu, Russell Aoki, Thomas Boyd, Eric W. Buddrius, Kevin Ceurter, Mustafa Haswarey, Rolf Laido, Daniel Neumann, Rachel Taylor, Anthony Valpiani
  • Patent number: 10418309
    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Bijoyraj Sahu, Thomas A. Boyd, Jeffory L. Smalley
  • Publication number: 20190223324
    Abstract: Systems, apparatuses, methods, and computer-readable media are presented for managing an apparatus for thermal energy management including a first container. The first container includes a first cavity, and is configured to hold a first liquid coolant within the first cavity to at least partially surround a second container. The second container includes a second cavity configured to hold one or more heat sources, and a second liquid coolant to at least partially surround the one or more heat sources. The second container is sealed to separate the first liquid coolant from the second liquid coolant. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Inventors: Minh Le, Thomas Boyd, Bijoyraj Sahu, Evan Chenelly, Christopher Wade Ackerman, Carlos Alvizo Flores, Craig Jahne
  • Patent number: 9889653
    Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: February 13, 2018
    Assignee: XEROX CORPORATION
    Inventors: Peter J. Nystrom, Andrew W. Hays, Bijoyraj Sahu
  • Publication number: 20150217568
    Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.
    Type: Application
    Filed: April 17, 2015
    Publication date: August 6, 2015
    Inventors: Peter J. Nystrom, Andrew W. Hays, Bijoyraj Sahu
  • Patent number: 9038269
    Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: May 26, 2015
    Assignee: XEROX CORPORATION
    Inventors: Peter J. Nystrom, Andrew W. Hays, Bijoyraj Sahu
  • Patent number: 8931879
    Abstract: A method for assembling a printhead such as an ink jet printhead can include the use of a laser to bond two or more printhead layers together. In an embodiment, a laser beam is directed through a transparent layer to an energy-absorbing layer, where the energy-absorbing layer is melted such that after removal of the laser beam the melted layer solidifies to adhere the energy-absorbing layer to the transparent layer. In another embodiment, heating the energy-absorbing layer melts the transparent layer to adhere the energy-absorbing layer to the transparent layer after removal of the laser beam. The laser transmission lamination process described can result in a fluid-tight seal which requires less processing time and materials over an adhesive-based process.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: January 13, 2015
    Assignee: Xerox Corporation
    Inventors: Peter J Nystrom, Mark A. Cellura, Bijoyraj Sahu
  • Patent number: 8919915
    Abstract: A method for assembling a printhead such as an ink jet printhead can include the use of an ultrasonic bonding process to bond two or more printhead layers together. In an embodiment, an ultrasonic frequency is directed to an interface between a first layer and a second layer to generate heat at the interface. In an embodiment, the heat melts at least one of the first layer and the second layer, and the layers are cooled to cure the melted layer. In another embodiment, the heat generated using the ultrasonic frequency cures an adhesive layer between the first layer and the second layer. The ultrasonic lamination process described can result in a fluid-tight seal which requires less processing time and materials over an adhesive-based process.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: December 30, 2014
    Assignee: Xerox Corporation
    Inventors: Peter J. Nystrom, Mark A. Cellura, Bijoyraj Sahu
  • Publication number: 20140295064
    Abstract: A nanoprinthead including an array of nanotip cantilevers, where each nanotip cantilever includes a nanotip at an end of a cantilever, and a method for forming the nanoprinthead. Each nanotip may be individually addressable through use of an array of piezoelectric actuators. Embodiments for forming a nanoprinthead including an array of nanotip cantilevers can include an etching process from a material such as a silicon wafer, or the formation of a metal or dielectric nanotip cantilever over a substrate. The nanoprinthead may operate to provide uses for technologies such as dip-pen nanolithography, nanomachining, and nanoscratching, among others.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 2, 2014
    Applicant: XEROX CORPORATION
    Inventors: Peter J. Nystrom, Andrew W. Hays, Bijoyraj Sahu
  • Patent number: 8727508
    Abstract: A print head including a jet stack can be formed using semiconductor device manufacturing techniques. A blanket metal layer, a blanket piezoelectric element layer, and a blanket conductive layer can be formed over a semiconductor substrate such as a semiconductor wafer or wafer section. The piezoelectric element layer and the blanket conductive layer can be patterned to provide a plurality of transducer piezoelectric elements and top electrodes respectively, while the metal layer forms a bottom electrode for the plurality of transducers. Subsequently, the semiconductor substrate can be patterned to form a body plate for the print head jet stack. Forming a print head jet stack using semiconductor device manufacturing techniques can provide a high resolution device with small feature sizes.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: May 20, 2014
    Assignee: Xerox Corporation
    Inventors: Peter J Nystrom, Bijoyraj Sahu