Abstract: According to one exemplary embodiment, a test device includes a transistor situated on a substrate. The test device further includes a protection device coupled by a fuse to a gate of the transistor in an interconnect metal layer, where the interconnect metal layer is formed over the substrate. The fuse allows the protection device to be decoupled from the gate of the transistor prior to testing the transistor. The test device further includes first and second contact pads formed over the substrate and coupled to respective terminals of the fuse to provide access to the fuse. A current can be applied between the first and second contacts pads to cause the fuse to open to decouple the protection device from the gate of the transistor. The test device further includes an antenna coupled to the gate of the transistor with interconnect metal segments for accumulating electrical charge during wafer processing.

Abstract: Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

Abstract: A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.