Patents by Inventor Bikram Baidya
Bikram Baidya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11468656Abstract: A method comprising identifying a plurality of non-overlapping coarse domains of a region of interest; selecting a subset of the plurality of coarse domains based on a plurality of first diversity metrics determined for the plurality of coarse domains; identifying a plurality of non-overlapping fine domains of the region of interest, wherein each of the fine domains is a portion of one of the coarse domains of the selected subset of the plurality of coarse domains; selecting a subset of the plurality of fine domains based on a plurality of second diversity metrics determined for the plurality of coarse domains; and providing an indication of the selected subset of the plurality of fine domains.Type: GrantFiled: June 29, 2019Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Bikram Baidya, Prasad N. Atkar, Vivek K. Singh, Md Ashraful Alam
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Patent number: 11301982Abstract: A method includes identifying a first geometric pattern that failed a design rule check, identifying a second geometric pattern that passed the design rule check, morphing the first geometric pattern based on the second geometric pattern to generate a morphed geometric pattern, wherein the morphed geometric pattern passes the design rule check, and replacing the first geometric pattern with the morphed geometric pattern.Type: GrantFiled: August 30, 2019Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Bikram Baidya, Hale Erten, Allan Gu, John A. Swanson, Vivek K. Singh, Abde Ali Hunaid Kagalwalla, Mengfei Yang-Flint
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Patent number: 11244440Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.Type: GrantFiled: August 30, 2019Date of Patent: February 8, 2022Assignee: Intel CorporationInventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Abde Ali Hunaid Kagalwalla
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Patent number: 11176658Abstract: A method comprising determining a binary classification value for each of a plurality of data instances based on a first threshold value assigned to each of the plurality of data instances; applying at least one clustering model to a first subset of the plurality of data instances to identify one or more dominant clusters of data instances; determining a second threshold value to assign to a second plurality of data instances that are included within the one or more dominant clusters of data instances; and redetermining a binary classification value for each of the plurality of data instances based on the second threshold value assigned to the second plurality of data instances and the first threshold value, wherein the first threshold value is assigned to at least a portion of data instances of the plurality of data instances that are not included in the second plurality of data instances.Type: GrantFiled: September 16, 2019Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Kumara Sastry, Abde Ali Hunaid Kagalwalla
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Patent number: 11010525Abstract: A search engine receives data describing reference geometry and generates a hash based on the reference geometry. A reference bloom filter is generated for the reference geometry based on the hash. The search engine performs a search to determine whether instances of the reference geometry are present in an integrated circuit (IC) layout. The search includes comparing the reference bloom filter with each one of a plurality of bloom filters corresponding to a plurality of subdomains of the IC layout. Based on results of the comparison, one or more subdomains of interest are identified and searched to determine whether the particular reference geometry is present in the subdomain.Type: GrantFiled: June 29, 2019Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Bikram Baidya, John A. Swanson, Prasad N. Atkar, Vivek K. Singh, Aswin Sreedhar
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Patent number: 10915691Abstract: A semantic pattern extraction system can distill tremendous amounts of silicon wafer manufacturing data to generate a small set of simple sentences (semantic patterns) describing physical design geometries that may explain manufacturing defects. The system can analyze many SEM images for manufacturing defects in areas of interest on a wafer. A tagged continuous itemset is generated from the images, with items comprising physical design feature values corresponding to the areas of interest and tagged with the presence or absence of a manufacturing defect. Entropy-based discretization converts the continuous itemset into a discretized one. Frequent set mining identifies a set of candidate semantic patterns from the discretized itemset. Candidate semantic patterns are reduced using reduction techniques and are scored. A ranked list of final semantic patterns is presented to a user. The final semantic patterns can be used to improve a manufacturing process.Type: GrantFiled: June 28, 2019Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Bikram Baidya, Vivek K. Singh, Allan Gu, Abde Ali Hunaid Kagalwalla, Saumyadip Mukhopadhyay, Kumara Sastry, Daniel L. Stahlke, Kritika Upreti
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Patent number: 10885259Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.Type: GrantFiled: August 30, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Bikram Baidya, John A. Swanson, Kumara Sastry, Prasad N. Atkar, Vivek K. Singh
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Publication number: 20200013161Abstract: A method comprising determining a binary classification value for each of a plurality of data instances based on a first threshold value assigned to each of the plurality of data instances; applying at least one clustering model to a first subset of the plurality of data instances to identify one or more dominant clusters of data instances; determining a second threshold value to assign to a second plurality of data instances that are included within the one or more dominant clusters of data instances; and redetermining a binary classification value for each of the plurality of data instances based on the second threshold value assigned to the second plurality of data instances and the first threshold value, wherein the first threshold value is assigned to at least a portion of data instances of the plurality of data instances that are not included in the second plurality of data instances.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Kumara Sastry, Abde Ali Hunaid Kagalwalla
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Publication number: 20200004921Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.Type: ApplicationFiled: August 30, 2019Publication date: January 2, 2020Inventors: Bikram Baidya, John A. Swanson, Kumara Sastry, Prasad N. Atkar, Vivek K. Singh
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Publication number: 20200005451Abstract: A method includes, for each data object of a plurality of data objects, performing a measurement on a plurality of instances of the data object to generate a plurality of measurement values for the data object, and generating a distribution of the measurement values for the data object. The method further includes generating an aggregate distribution based on each of the distributions of the measurement values generated for the data objects, and scoring a first data object of the plurality of data objects based on the distribution of the measurement values for the first data object and the aggregate distribution.Type: ApplicationFiled: August 30, 2019Publication date: January 2, 2020Applicant: Intel CorporationInventors: Bikram Baidya, Allan Gu, Vivek K. Singh, Abde Ali Hunaid Kagalwalla
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Publication number: 20190385300Abstract: A method includes identifying a first geometric pattern that failed a design rule check, identifying a second geometric pattern that passed the design rule check, morphing the first geometric pattern based on the second geometric pattern to generate a morphed geometric pattern, wherein the morphed geometric pattern passes the design rule check, and replacing the first geometric pattern with the morphed geometric pattern.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: Bikram Baidya, Hale Erten, Allan Gu, John A. Swanson, Vivek K. Singh, Abde Ali Hunaid Kagalwalla, Mengfei Yang-Flint
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Publication number: 20190325246Abstract: A method comprising identifying a plurality of non-overlapping coarse domains of a region of interest; selecting a subset of the plurality of coarse domains based on a plurality of first diversity metrics determined for the plurality of coarse domains; identifying a plurality of non-overlapping fine domains of the region of interest, wherein each of the fine domains is a portion of one of the coarse domains of the selected subset of the plurality of coarse domains; selecting a subset of the plurality of fine domains based on a plurality of second diversity metrics determined for the plurality of coarse domains; and providing an indication of the selected subset of the plurality of fine domains.Type: ApplicationFiled: June 29, 2019Publication date: October 24, 2019Inventors: Bikram Baidya, Prasad N. Atkar, Vivek K. Singh, Md Ashraful Alam
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Publication number: 20190325103Abstract: A search engine receives data describing reference geometry and generates a hash based on the reference geometry. A reference bloom filter is generated for the reference geometry based on the hash. The search engine performs a search to determine whether instances of the reference geometry are present in an integrated circuit (IC) layout. The search includes comparing the reference bloom filter with each one of a plurality of bloom filters corresponding to a plurality of subdomains of the IC layout. Based on results of the comparison, one or more subdomains of interest are identified and searched to determine whether the particular reference geometry is present in the subdomain.Type: ApplicationFiled: June 29, 2019Publication date: October 24, 2019Inventors: Bikram Baidya, John A. Swanson, Prasad N. Atkar, Vivek K. Singh, Aswin Sreedhar
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Publication number: 20190318059Abstract: A semantic pattern extraction system can distill tremendous amounts of silicon wafer manufacturing data to generate a small set of simple sentences (semantic patterns) describing physical design geometries that may explain manufacturing defects. The system can analyze many SEM images for manufacturing defects in areas of interest on a wafer. A tagged continuous itemset is generated from the images, with items comprising physical design feature values corresponding to the areas of interest and tagged with the presence or absence of a manufacturing defect. Entropy-based discretization converts the continuous itemset into a discretized one. Frequent set mining identifies a set of candidate semantic patterns from the discretized itemset. Candidate semantic patterns are reduced using reduction techniques and are scored. A ranked list of final semantic patterns is presented to a user. The final semantic patterns can be used to improve a manufacturing process.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Bikram Baidya, Vivek K. Singh, Allan Gu, Abde Ali Hunaid Kagalwalla, Saumyadip Mukhopadhyay, Kumara Sastry, Daniel L. Stahlke, Kritika Upreti
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Patent number: 9268893Abstract: Photolithography mask synthesis is disclosed for spacer patterning masks. In one example, backbone features are extracted from a target layout of a mask design. A connectivity graph is generated based on the target layout in which lines of the backbone features are represented as nodes on the connectivity graph. The nodes are connected based on spacer patterning process limitations and the connections are assigned to sets. A backbone mask layout is then generated based on one of the sets of nodes.Type: GrantFiled: December 29, 2011Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Bikram Baidya, Omkar S. Dandekar, Vivek K. Singh
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Publication number: 20150095859Abstract: Photolithography mask synthesis is disclosed for spacer patterning masks. In one example, backbone features are extracted from a target layout of a mask design. A connectivity graph is generated based on the target layout in which lines of the backbone features are represented as nodes on the connectivity graph. The nodes are connected based on spacer patterning process limitations and the connections are assigned to sets. A backbone mask layout is then generated based on one of the sets of nodes.Type: ApplicationFiled: December 29, 2011Publication date: April 2, 2015Inventors: Bikram Baidya, Omkar S. Dandekar, Vivek K. Singh
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Patent number: 8778605Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.Type: GrantFiled: February 7, 2013Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Shem Ogadhoh, Raguraman Venkatesan, Kevin J. Hooker, Sungwon Kim, Bin Hu, Vivek Singh, Bikram Baidya, Prasad Narendra Atkar, Seongtae Jeong
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Publication number: 20130149638Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.Type: ApplicationFiled: February 7, 2013Publication date: June 13, 2013Inventors: Shem OGADHOH, Raguraman VENKATESAN, Kevin J. HOOKER, Sungwon KIM, Bin HU, Vivek SINGH, Bikram BAIDYA, Prasad NARENDRA ATKAR, Seongtae JEONG
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Patent number: 8404403Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.Type: GrantFiled: June 25, 2010Date of Patent: March 26, 2013Assignee: Intel CorporationInventors: Shem Ogadhoh, Raguraman Venkatesan, Kevin J. Hooker, Sungwon Kim, Bin Hu, Vivek Singh, Bikram Baidya, Prasad Narendra Atkar, Seongtae Jeong
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Publication number: 20110318672Abstract: Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Inventors: Shem Ogadhoh, Raguraman Venkatesan, Kevin J. Hooker, Sungwon Kim, Bin Hu, Vivek Singh, Bikram Baidya, Prasad Narendra Atkar, Seongtae Jeong