Patents by Inventor Bill Beane

Bill Beane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for monitoring and controlling binary state devices using a memory device
    Patent number: 7904667
    Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: March 8, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yunsheng Wang, Casey Springer, Tak Kwong Wong, Bill Beane
  • Systems and methods for monitoring and controlling binary state devices using a memory device
    Patent number: 7747828
    Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: June 29, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yunsheng Wang, Casey Springer, Tak Kwong Wong, Bill Beane
  • Collision detection in a multi-port memory system
    Patent number: 7363436
    Abstract: A collision detection circuit for a multi-port memory system is presented. The collision detection circuit detects a collision condition if the addresses at two or more ports at the same time match and if one of the two or more ports is writing to the memory location associated with that address. A collision flag can then be set when the collision condition exists. In some embodiments, arbitration can occur when the collision flag is set.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: April 22, 2008
    Assignee: Integrated Device Technology, Inc.
    Inventors: Tzong-Kwang Henry Yeh, Bill Beane, Chung Han Lin, Wei-Ling Chang
  • Systems and methods for monitoring and controlling binary state devices using a memory device
    Publication number: 20060277372
    Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
    Type: Application
    Filed: August 10, 2006
    Publication date: December 7, 2006
    Inventors: Yunsheng Wang, Casey Springer, Tak Wong, Bill Beane
  • Systems and methods for monitoring and controlling binary state devices using a memory device
    Publication number: 20060106989
    Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
    Type: Application
    Filed: November 17, 2004
    Publication date: May 18, 2006
    Inventors: Yunsheng Wang, Casey Springer, Tak Wong, Bill Beane