Patents by Inventor Bill Bereza
Bill Bereza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7697603Abstract: Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.Type: GrantFiled: October 18, 2004Date of Patent: April 13, 2010Assignee: Altera CorporationInventors: Shoujun Wang, Tad Kwasniewski, Bill Bereza
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Patent number: 7580497Abstract: A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.Type: GrantFiled: June 29, 2005Date of Patent: August 25, 2009Assignee: Altera CorporationInventors: Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
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Patent number: 7528635Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.Type: GrantFiled: February 23, 2007Date of Patent: May 5, 2009Assignee: Altera CorporationInventors: Tad Kwasniewski, Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza
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Patent number: 7486752Abstract: A received clock signal is aligned (“eye centered”) with a received data signal by recovering a separate clock from the data signal and comparing and aligning the received clock with the recovered clock by delaying one or both of the received clock and the received data as necessary. After the necessary delays are set, the comparison/alignment circuitry can be turned off, until the next time alignment is necessary, to conserve power. In a multiple channel system, any combination of each received data channel, the received clock, or individual branches of the received clock in each channel can be delayed as necessary. Each channel can have its own comparison/alignment circuitry so that all channels can be aligned simultaneously, or re-usable circuitry can be provided for connection sequentially to each channel where sequential alignment of the channels is fast enough.Type: GrantFiled: December 17, 2003Date of Patent: February 3, 2009Assignee: Altera CorporationInventors: Tad Kwasniewski, Bill Bereza, Shoujun Wang, Mashkoor Baig, Haitao Mei
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Patent number: 7453294Abstract: A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.Type: GrantFiled: June 28, 2005Date of Patent: November 18, 2008Assignee: Altera CorporationInventors: Shoujun Wang, Haitao Mei, Bill Bereza
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Patent number: 7388443Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.Type: GrantFiled: April 25, 2006Date of Patent: June 17, 2008Assignee: Altera CorporationInventors: Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
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Publication number: 20070241795Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.Type: ApplicationFiled: February 23, 2007Publication date: October 18, 2007Applicant: Altera CorporationInventors: Tad Kwasniewski, Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza
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Publication number: 20070237186Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.Type: ApplicationFiled: April 11, 2006Publication date: October 11, 2007Inventors: Sergey Shumarayev, Bill Bereza, Chong Lee, Rakesh Patel, Wilson Wong
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Patent number: 7239849Abstract: Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.Type: GrantFiled: November 4, 2003Date of Patent: July 3, 2007Assignee: Altera CorporationInventors: Bill Bereza, Mashkoor Baig, Shoujun Wang, Haitao Mei, Tad Kwasniewski
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Patent number: 7224191Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.Type: GrantFiled: November 17, 2006Date of Patent: May 29, 2007Assignee: Altera CorporationInventors: Shoujun Wang, Bill Bereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei
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Patent number: 7196557Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.Type: GrantFiled: January 13, 2004Date of Patent: March 27, 2007Assignee: Altera CorporationInventors: Tad Kwasniewski, Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza
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Publication number: 20070002993Abstract: A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.Type: ApplicationFiled: June 29, 2005Publication date: January 4, 2007Inventors: Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
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Patent number: 7157944Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.Type: GrantFiled: April 27, 2004Date of Patent: January 2, 2007Assignee: Altera CorporationInventors: Shoujun Wang, Bill Bereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei
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Patent number: 7143312Abstract: A recovered clock signal is aligned (“eye centered”) with a data signal from which it is recovered by intentionally varying one of the factors or parameters that causes misalignment. For example, if a loop circuit (i.e., a phase-locked loop or a delay-locked loop) is used to recover the clock signal, charge pump current mismatch in the charge pump of the loop circuit is normally one factor in clock-data misalignment, and is also a parameter that can be manipulated. During a test mode, the current mismatch can be varied to obtain the best error rate, which signifies the best clock-data alignment. The test mode can be implemented using built-in self-test circuitry already on the device to transmit test data and then to receive it and analyze it for errors.Type: GrantFiled: December 17, 2003Date of Patent: November 28, 2006Assignee: Altera CorporationInventors: Shoujun Wang, Haitao Mei, Bill Bereza, Mashkoor Baig, Tad Kwasniewski
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Publication number: 20060192623Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.Type: ApplicationFiled: April 25, 2006Publication date: August 31, 2006Inventors: Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
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Patent number: 7061334Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.Type: GrantFiled: June 3, 2004Date of Patent: June 13, 2006Assignee: Altera CorporationInventors: Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
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Patent number: 6970020Abstract: A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component signals can be combined to provide the expected UP and DOWN phase detector output control signals. The phase detector output signals are balanced and of uniform width, minimizing oscillator control signal ripple in the clock data recovery circuit, while the linearity of the phase detector makes its output predictable.Type: GrantFiled: December 17, 2003Date of Patent: November 29, 2005Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, Mashkoor Baig, Bill Bereza, Tad Kwasniewski
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Patent number: 6956407Abstract: Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is switched to connect only to the node to which the current circuits were not previously connected if there has been no further transition in the input data signal during the time delay. If only single-ended (i.e., non-differential) output is desired, only one of the output nodes is used as an output signal source. More than two current circuits may be used, and their switching from one node to the other may be performed progressively to provide pre-emphasis having any of many different characteristics.Type: GrantFiled: November 4, 2003Date of Patent: October 18, 2005Assignee: Altera CorporationInventors: Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski
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Publication number: 20050160327Abstract: Systems and methods for correcting distortions in transmitted signals are provided. More particularly, systems and methods for correcting the asymmetry that may occur between a receiver's signal-eye and a distorted signal are provided. One technique centers the signal-eye, with respect to the received signal, by adjusting the voltage threshold of the signal-eye in the receiver's clock and data recovery decision circuit. Another technique centers the signal-eye, with respect to the received signal, by shaping the voltage of the received signal. A current-mode logic circuit is provided to shape the voltage of the received signal by sinking current from the received signal.Type: ApplicationFiled: January 13, 2004Publication date: July 21, 2005Inventors: Mashkoor Baig, Shoujun Wang, Tad Kwasniewski, Haitao Mei, Bill Bereza
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Publication number: 20050093580Abstract: Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is switched to connect only to the node to which the current circuits were not previously connected if there has been no further transition in the input data signal during the time delay. If only single-ended (i.e., non-differential) output is desired, only one of the output nodes is used as an output signal source. More than two current circuits may be used, and their switching from one node to the other may be performed progressively to provide pre-emphasis having any of many different characteristics.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Inventors: Mashkoor Baig, Shoujun Wang, Haitao Mei, Bill Bereza, Tad Kwasniewski