Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.

Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.

Abstract: CMOS image sensor with LED flickering reduction and low color cross-talk are disclosed. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of large subpixels (LPDs) and at least one small subpixel (SPD). A plurality of color filters are disposed over individual subpixels. Each individual SPD is laterally adjacent to at least one other SPD.

Abstract: Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.

Abstract: A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region.

Abstract: A backside-illuminated image sensor includes arrayed photodiodes separated by isolation structures, and interlayer dielectric between first layer of metal interconnect and substrate. The image sensor has barrier metal walls in the interlayer dielectric between isolation structures and first layer interconnect, the barrier metal walls aligned with the isolation structures and disposed between the isolation structures and first layer interconnect. The barrier metal wall deflects light passing through photodiodes of the sensor that would otherwise be reflected by interconnect into different photodiodes.

Abstract: An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. At least three substrate trench structures are formed in the semiconductor substrate, defining two nonplanar structures, each having a plurality of sidewall portions. An isolation layer includes at least three isolation layer trench structures, each being disposed in a respective one of the three substrate trench structures. A gate includes three fingers, each being disposed in a respective one of the three isolation layer trench structures. An electron channel of the transistor extends along the plurality of sidewall portions of the two nonplanar structures in a channel width plane.

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. The transistor includes a nonplanar structure disposed in the semiconductor substrate, which is bounded by two outer trench structures formed in the semiconductor substrate. Isolation deposits are disposed within the two outer trench structures formed in the semiconductor substrate. A gate includes a planar gate and two fingers extending into one of two inner trench structures formed in the semiconductor substrate between the nonplanar structure and a respective one of the two outer trench structures. This structure creates an electron channel extending along a plurality of sidewall portions of the nonplanar structure in a channel width plane.

Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.

Abstract: A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.

Abstract: CMOS image sensor with LED flickering reduction and low color cross-talk are disclosed. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of large subpixels (LPDs) and at least one small subpixel (SPD). A plurality of color filters are disposed over individual subpixels. Each individual SPD is laterally adjacent to at least one other SPD.

Abstract: An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

Abstract: Examples of the disclosed subject matter propose disposing deep trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. In some example embodiments, the deep trench isolation structure extends into the semiconductor substrate from the back side of the semiconductor substrate and abuts against or contacts the bottom of shallow trench isolation structure disposed in the front side of the semiconductor substrate. Together, the trench isolating structure isolates the transistor channel of the pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, such as a floating P-doped well region (P-well), containing a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.

Abstract: A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.

Abstract: An image sensor with quantum efficiency enhanced by inverted pyramids includes a semiconductor substrate and a plurality of microlenses. The semiconductor substrate includes an array of pixels. Each of the pixels is configured to convert light incident on the pixel to an electrical output signal, the semiconductor substrate having a top surface for receiving the light. The top surface forms a plurality of inverted pyramids in each pixel. The plurality of microlenses are disposed above the top surface and aligned to the plurality of inverted pyramids, respectively.

Abstract: Image sensors include a substrate material having a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) disposed therein. A plurality of pixel isolators is formed in the substrate material, each pixel isolator being disposed between one of the SPDs and one of the LPDs. A passivation layer is disposed on the substrate material and a buffer layer is disposed on the passivation layer. A plurality of first metal elements is disposed in the buffer layer, each first metal element being disposed over one of the pixel isolators, and a plurality of second metal elements is disposed over the plurality of first metal elements.

Abstract: A pixel cell includes a first photodiode, a second photodiode, a first deep trench isolation region, a second deep trench isolation region, a buffer oxide layer, and a light attenuation layer. The attenuation layer partially encapsulates the first photodiode by extending laterally from the first deep trench isolation region to the second deep trench isolation region between the semiconductor material and the buffer oxide layer.

Abstract: Examples of the disclosed subject matter propose disposing deep trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. In some example embodiments, the deep trench isolation structure extends into the semiconductor substrate from the back side of the semiconductor substrate and abuts against or contacts the bottom of shallow trench isolation structure disposed in the front side of the semiconductor substrate. Together, the trench isolating structure isolates the transistor channel of the pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, such as a floating P-doped well region (P-well), containing a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.