Abstract: A fast frame store incorporating a memory array having selectable memory banks which include a plurality of relatively slow dynamic RAMs (DRAMs) is disclosed. The frame store has a buffered input and a buffered output to slow the data rate. Data can be read in parallel into a selected memory bank while at the same time other data are being read in parallel out of another selected memory bank. Refresh of DRAMs of an unselected bank occurs simultaneously with the transfer of data to or from the frame store. Several memory banks of the frame store are connected to a single row address select (RAS) line, so that when a selected bank is being addressed for data transfer, the memory location of several other unselected banks are being refreshed.

Abstract: A unit transformation circuit transforms three discrete input signals into a set of transform coefficient signals characteristic of a "collapsed" Walsh-Hadamard transform. The unit transformation circuit includes two tiers of arithmetic networks. In the first tier, a pair of arithmetic networks generates (A) first sum and difference signals from the first and second input signals and (B) second sum and difference signals from the second and third input signals. Arithmetic networks in the second tier generate a set of coefficient signals from (A) the sum of the first and second sum signals (B) the sum of the first and second difference signals and (C) the difference between the first and second difference signals. The unit transformation circuit forms a fundamental circuit element from which more complex circuits are constructed capable of transforming larger numbers of discrete input signals.