Abstract: A complexity determining apparatus is disclosed which comprises a source of a data signal and a subsampler system, coupled to the data signal source, for producing a subsampled signal representing the data signal. A variable bit rate (VBR) encoder is responsive to the subsampled signal and produces an encoded signal representing the subsampled signal. A counter accumulates the number of bits in the encoded signal and produces a complexity representative signal corresponding to the accumulated number of bits.

Abstract: A digital video system receives a digital bitstream representing video and audio information and containing a plurality of packetized data programs in a data format and includes data units related to the selection of individual programs and individual packetized datastreams associated with a program. The system includes a first processor responsive to the bitstream for capturing program guide information and a second processor responsive to the bitstream for capturing selected program data. The program guide data includes a base data unit for selecting a first program and a second data unit of predetermined offset to the base data unit for selecting a second program. The second processor captures program data by capturing data with identifiers matching an identifier determined from the data units.

Abstract: An MPEG compatible decoder receives encoded, compressed data in the form of image representative pixel blocks. The decoder includes a frame memory (20) for storing reconstructed pixel blocks incident to the decoding process. The previously decompressed data is re-compressed (30) before being written to the memory. Stored decompressed data is decompressed for display (34, 26), or as needed for decoding functions such as motion compensation processing (32, 22). The compression performed before writing data to memory is block-based compression using compressed data from one of two different compression paths (FIG. 3, 314, 320) which compress a given pixel block simultaneously.

Abstract: A television receiver with an MPEG decoder is configurable for full high definition decoding and display, or reduced cost lower definition display. The MPEG decoder (10-33) uses a controllable dual-mode data reduction network selectively employing horizontal detail reduction (29) and data re-compression (30) between the decoder and the decoder frame memory (20) from which image information to be displayed (27) is derived. The amount of data reduction is manufacturer selected in accordance with the resolution of the display device, e.g., equal to or less than high definition resolution. The frame memory size is also manufacturer selected in accordance with the resolution of the display device.

Abstract: A television receiver with an MPEG decoder is configurable for full high definition decoding and display, or reduced cost lower definition display. The MPEG decoder (10-33) uses a controllable dual-mode data reduction network selectively employing horizontal detail reduction (29) and data re-compression (30) between the decoder and the decoder frame memory (20) from which image information to be displayed (27) is derived. The amount of data reduction is manufacturer selected in accordance with the resolution of the display device, e.g., equal to or less than high definition resolution. The frame memory size is also manufacturer selected in accordance with the resolution of the display device.

Abstract: A color interpolation circuit allows information uniquely identifying one of six colors to be stored by using only two binary bits of memory storage, and allows information uniquely identifying one of 120 colors to be stored by using only four binary bits of memory storage. This is accomplished by storing only the foreground, edge, and background colors (i.e., herein referred to as "independent" colors), and an "interpolate operator" code, and by providing circuitry to properly interpret and process the interpolate operator code to generate "intermediate colors". This permits a 33% reduction of memory size and reduces the "fetch speed" requirements of associated on-screen display (OSD) scan converter circuitry.

Abstract: A television system for receiving a plurality of digitally-encoded television programs includes circuitry for selecting a particular digital data transmission channel from a plurality of digital data transmission channels containing a desired digitally-encoded television program in response to a control signal, at least one of the data transmission channels also including television program schedule data. The system also includes user-operable data entry circuitry for entering data, and a controller for generating the above-noted control signal in response to user-entered data. The controller selects a virtual channel from a plurality of virtual channels in response to user-entered data, each virtual channel being subject to reassignment to a different one of said a plurality of digital data transmission channels, the television program schedule data defining the relationship of each of the television programs to respective ones of the plurality of digital data transmission channels.

Abstract: In a timekeeping arrangement, including seconds, minutes and hours counters and associated display decoding circuitry, during temporary power line dropouts, the supply voltage for the hours and minutes counters is maintained by an associated voltage storage capacitor so that their contents are retained, and, upon the return of line power, the seconds counter is set to a number corresponding to 30 seconds. In this manner, over a number of random temporary power dropouts, the accuracy of the timekeeping arrangement is maintained without the need of readjustment or the use of auxiliary systems powered by standby power sources.

Abstract: A circuit for storing a DC voltage which may be used to control the volume, brightness, contrast, tint or color characteristics of a television receiver includes a semiconductor switching circuit for selectively coupling a DC voltage to a voltage storage capacitor through a DC impedance path. The DC impedance path is coupled between the inverting and noninverting inputs of an operational amplifier. The output of the operational amplifier is coupled to a utilization circuit to be controlled. A feedback path is coupled between the operational amplifier's output and inverting input to provide negative feedback so that a voltage balance is maintained between the inverting and noninverting inputs and thereby substantially eliminate leakage current flow to or from the storage capacitor through the DC impedance path.

Abstract: A wide bandwidth, ultrasonic frequency transducer drive circuit incorporates a first unidirectional signal path from a source of drive signals to the transducer. A second unidirectional signal path from the source of drive signals couples signals away from the transducer. A circuit resonant with the transducer causes a relatively high signal voltage to be developed across this transducer.

Abstract: Alphanumeric characters having borders of different color or brightness from the body of the characters are generated on a raster scan display device. Signals are generated for forming a first character having size equal to the character and borders. A second, smaller character is generated from the signals of the first, by appropriately blanking portions of the first character signals. The first and second character signals are arranged to produce centered, overlapping images of different colors or brightnesses on the display device.

Abstract: An ion current is produced between two spatially separated electrodes by creating a corona discharge about one of these electrodes and causing ions to flow to the other electrode. Aerosols introduced into the region between the two electrodes interact with the flowing ions causing a resultant decrease in ion current. A decrease in ion current is sensed to indicate the presence of aerosols.