Patents by Inventor Bing Xue

Bing Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160170396
    Abstract: A method for implementing energy saving for a mixed insertion system (80) of rectifiers with different power includes: acquiring work-related input information, and identifying a type of a rectifier (100); determining a power-on/power-off control mode of each rectifier (200); and performing power-on/power-off rotation, and load change rotation (400) and periodic rotation (500) starting according to the power-on/power-off control mode of each rectifier (300). A mixed insertion system of rectifiers with different power and a device for implementing energy saving thereof are further disclosed.
    Type: Application
    Filed: April 22, 2014
    Publication date: June 16, 2016
    Inventors: Wei WANG, Dongbo LIU, Bing XUE
  • Patent number: 6484958
    Abstract: A caddy for dispensing fiber optic patch cord cables. The device has a housing inside of which a disk is rotatably mounted. A length of patch cord cable is wound around the circumference of the disk and an S-shaped channel is present on one side of the disk. The channel is sized to hold captive a section of the patch cord fiber optic cable, thereby preventing any loss of signal or damage to the patch cord fiber optic cable from undue bending stresses on the cable. The housing has an opening through which the two ends of the patch cord fiber optic cable protrude.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 26, 2002
    Assignee: Dowslake Microsystems Corporation
    Inventors: Bing Xue, Stefan Ignaczak, Dan Dan Yang
  • Patent number: 5630021
    Abstract: A Hamming neural network circuit is provided with N binary inputs and M exemplar template outputs, and has a template matching calculation subnet and a winner-take-all subnet. The template matching calculation subnet includes M first neurons in which M exemplar templates are stored respectively. Each first neuron includes N pull-up and pull-down transistor pairs connected in parallel with each other, and connected to and controlled by the N binary inputs, respectively, so that the M first neurons generate M template matching signals depending on the matching degrees between the N binary inputs and the M exemplar templates. The winner-take-all subnet includes M second neurons, each having a template competition node, a load element connected between a power source and the template competition node, and a competition circuit connected between the template competition node and ground.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: May 13, 1997
    Assignee: United Microelectronics Corp.
    Inventors: Zhi-Jian Li, Bing-Xue Shi, Bin-Qiao Li
  • Patent number: 5544279
    Abstract: A fuzzy logic recognition device has a plurality of sets of feature extraction windows, each set storing the predetermined features for one feature class therein, and comparing the stored features with the corresponding features of an unknown recognition mode to output a logic "1" via one corresponding feature extraction window where an identicalness condition occurs, and logic "0" via the other feature extraction windows where no identicalness condition occurs. A plurality of sets of membership function generators are coupled to the feature extraction window sets respectively. Each membership function generator which receives the logic "1" generates the memberships of the corresponding feature with respect to the target modes, and the membership function generators which receive the logic "0" do not generate the memberships.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: August 6, 1996
    Assignee: United Microelectronics Corp.
    Inventors: Zhi-Jian Li, Bing-Xue Shi, Bin-Qiao Li
  • Patent number: 5444821
    Abstract: A neuron element with electrically programmable synaptic weight for an artificial neural network features an excitatory-connection floating-gate transistor and an inhibitory-connection floating-gate transistor. The control gate electrodes of the two transistors are connected together, and the drain electrode of the inhibitory-connection transistor is connected to the source electrode of the excitatory-connection transistor. Both of the excitatory-connection and inhibitory-connection transistors have programming electrodes. The control gate electrodes and the programming electrodes can be utilized to program the threshold voltages of the transistors and thus the synaptic weight of the neuron element.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: August 22, 1995
    Assignee: United Microelectronics Corp.
    Inventors: Zhi-Jian Li, Bing-Xue Shi, Yang Wang