Abstract: An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.

Abstract: An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.

Abstract: An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.

Abstract: An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.

Abstract: A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The method includes the steps of defining a plurality of cells to be provided along the wide interface of the circuitry, further devices being associated with at least one of the cells, and defining the circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. The method includes the steps of: providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block, where the rules take into account the location of the block in the array and any association between the further devices and the cells.

Abstract: An integrated circuit is provided with a power domain which can be selectively powered-up or powered-down. An output circuitry serving to buffer a signal generated by the core circuitry within such a power domain has its own output power supply voltage. An adaptive voltage sensing circuit senses when the core power supply voltage to the core circuitry falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a pulse with its value stored within a mode latch indicating whether or not retention is required. Thus, when the adapted voltage sensing circuitry itself senses the voltage level for the core circuitry falling below the threshold, it activates the retention operation.

Abstract: A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The interconnect circuitry on a first side provides a narrow interface for connection to a first device, and on a second side provides a wide interface for connection to a distributed plurality of further devices. Each data path is associated with one of the further devices and provides a connection through the interconnect circuitry between that associated further device and the first device. The method comprises the steps of defining a plurality of cells to be provided along the wide interface, each of the further devices being associated with at least one of the cells, and defining the interconnect circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns.

Abstract: An integrated circuit is provided with a power domain PD0, PD1, PD2, PD3 which can be selectively powered-up or powered-down. An output circuitry 8 serving to buffer a signal 12 generated by the core circuitry 10 within such a power domain has its own output power supply voltage IOVdd. An adaptive voltage sensing circuit 24 senses when the core power supply voltage to the core circuitry 10 falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry 8 responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a on-shot pulse with its value stored within a mode latch 24 indicating whether or not retention is required.