Patents by Inventor Binh Ngo

Binh Ngo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141385
    Abstract: This invention provides methods and systems for enhancement of protein production from mammalian cell lines in a drug inducible manner. The methods described herein can be used to generate a protein production cell line wherein the gene coding the protein product of interest is inserted into specific safe harbor loci (SHL) within the cell's genome and the gene copy number is induced to amplify by the use of an antibiotic inducer. The method enables for the conditional activation of the drug inducible transposase. The drug inducible gene amplification method described herein effectively functions as a molecular dial: combining drug-inducible homologous recombination and conditional gene activation to fine-tune gene amplification in mammalian systems.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Inventors: Kathy Ngo, Jennifer Woo, Binh Pham, Vu Truong-Le
  • Publication number: 20230317144
    Abstract: An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Applicant: Intel NDTM US LLC
    Inventors: Chang Wan Ha, Binh Ngo, Ali Khakifirooz, Aliasgar S. Madraswala, Bharat Pathak, Pranav Kalavade, Shantanu Rajwade
  • Publication number: 20230178158
    Abstract: Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Soo-yong Park, Pranav Chava, Binh Ngo
  • Publication number: 20230138471
    Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to monitor a sense voltage for an operation associated with a wordline of the NAND memory, and adjust a negative charge pump for the wordline prior to completion of the operation based on the monitored sense voltage. Other examples are disclosed and claimed.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Applicant: Intel NDTM US LLC
    Inventors: Binh Ngo, Moonkyun Maeng, Navid Paydavosi, Sagar Upadhyay, Sanket Sanjay Wadyalkar, Soo-yong Park
  • Publication number: 20230123096
    Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to control access to the NAND memory as two or more groups of memory cells, provide independent operations for the two or more groups of memory cells, share a voltage regulator among at least two of the two or more groups of memory cells, and provide a target constant voltage from the shared voltage regulator to a target group of the two or more groups of memory cells in an independent operation for the target group. Other examples are disclosed and claimed.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Applicant: Intel NDTM US LLC
    Inventors: Moonkyun Maeng, Anup Suresh Patil, Louis Ahn, Binh Ngo
  • Publication number: 20230079077
    Abstract: Technology herein provides a performance-enhanced memory device including a memory array including a local word line circuit and a plurality of local word lines coupled to the local word line circuit, a word line (WL) sense circuit coupled to an access node in the local word line circuit, the WL sense circuit to sense a voltage level in the local word line circuit while bypassing a disturbance to operation of the local word lines and to provide an output signal that indicates when the voltage level has reached a high voltage threshold value to enable a read operation. The technology also provides read logic coupled to the WL sense circuit, the read logic to receive the output signal from the WL sense circuit, and trigger a read operation for one or more cells in the memory array when the output signal indicates that the voltage level has reached the high voltage threshold value.
    Type: Application
    Filed: October 17, 2022
    Publication date: March 16, 2023
    Inventors: Saied Hemati, Binh Ngo
  • Publication number: 20230082368
    Abstract: Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Chang Wan Ha, Binh Ngo, Ahsanur Rahman, Radhika Chinnammagari, Sagar Upadhyay
  • Publication number: 20220415380
    Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Naveen Prabhu Vittal Prabhu, Aliasgar S. Madraswala, Bharat Pathak, Binh Ngo, Netra Mahuli, Ahsanur Rahman