Abstract: Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.

Abstract: One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

Abstract: An example radio receiver and a method is provided for controlling a radio receiver having two tuners, and receiving a hybrid signal containing digital and analog broadcast signal components. According to the example method, a selection is made in the radio receiver to operate between at least the following operating modes of the receiver: (i) a first operating mode in which both tuners are tuned to the same broadcast hybrid signal and where one of the tuners is configured to receive the digital broadcast signal and the other tuner is configured to receive the analog broadcast signal; (ii) a second operating mode in which one of the tuners receiving the digital broadcast signal is the operating tuner and the other tuner is a search and check tuner; and (iii) a third operating mode in which one of the tuners receiving the analog broadcast signal is the operating tuner and the other tuner is a search and check tuner.

Abstract: A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.

Abstract: An example radio receiver and a method is provided for controlling a radio receiver having two tuners, and receiving a hybrid signal containing digital and analog broadcast signal components. According to the example method, a selection is made in the radio receiver to operate between at least the following operating modes of the receiver: (i) a first operating mode in which both tuners are tuned to the same broadcast hybrid signal and where one of the tuners is configured to receive the digital broadcast signal and the other tuner is configured to receive the analog broadcast signal; (ii) a second operating mode in which one of the tuners receiving the digital broadcast signal is the operating tuner and the other tuner is a search and check tuner; and (iii) a third operating mode in which one of the tuners receiving the analog broadcast signal is the operating tuner and the other tuner is a search and check tuner.

Abstract: Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.

Abstract: An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.

Abstract: Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.

Abstract: Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.