Abstract: This application provides a photovoltaic system and a maximum power point tracking control method for a photovoltaic system. The photovoltaic system includes an MPPT controller and a power converter, and the MPPT controller is connected to the power converter. The MPPT controller is configured to: be connected to a photovoltaic array, and track a global maximum power point MPP of the photovoltaic array. The MPPT controller may be further configured to obtain, when there is a periodic shade for the photovoltaic array, a multi-peak search start moment of global MPPT of the photovoltaic array based on a status of tracking the global MPP of the photovoltaic array in a target time period, so that when the multi-peak search start moment in each MPPT period arrives, the global MPPT of the photovoltaic array is started, to output a working point of the global MPP of the photovoltaic array to the power converter.

Abstract: This application provides a photovoltaic system and a maximum power point tracking control method for a photovoltaic system. The photovoltaic system includes an MPPT controller and a power converter, and the MPPT controller is connected to the power converter. The MPPT controller is configured to: be connected to a photovoltaic array, and track a global maximum power point MPP of the photovoltaic array. The MPPT controller may be further configured to obtain, when there is a periodic shade for the photovoltaic array, a multi-peak search start moment of global MPPT of the photovoltaic array based on a status of tracking the global MPP of the photovoltaic array in a target time period, so that when the multi-peak search start moment in each MPPT period arrives, the global MPPT of the photovoltaic array is started, to output a working point of the global MPP of the photovoltaic array to the power converter.

Abstract: The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Abstract: A direct-current electric arc detection method and apparatus, a device, a system, and a storage medium. The method includes: obtaining an electrical quantity of a direct current circuit; inputting the electrical quantity into a burning arc neural network model to perform burning arc detection on the direct current circuit, to obtain a burning arc detection result; and if the burning arc detection result is that a burning arc is detected, determining that a direct-current electric arc fault exists in the direct current circuit. Because the electrical quantity is input into the burning arc neural network model to perform burning arc detection on the direct current circuit, a direct-current electric arc fault is detected, and accuracy of detecting a direct-current electric arc fault is further improved.

Abstract: The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.