Patents by Inventor Birendra Nath

Birendra Nath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7125724
    Abstract: The present invention relates to a method for identification and/or diagnosis of REM sleep loss. More particularly, the present invention relates to a method for identification and/or diagnosis of REM sleep loss from blood samples.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: October 24, 2006
    Assignee: Jawaharlal Nehru University
    Inventors: Birendra Nath Mallick, Santosh Kumar Kar, Bibhuti Bhusan Mishra, Vibha Madan
  • Patent number: 6840309
    Abstract: A heat exchanger comprising a pressure vessel (1). A plurality of serpentines (8) convey a fluid to be heated through the pressure vessel (1) in one direction. A duct (9) surrounding the serpentines (8) conveys a second fluid in the opposite direction to give up its heat to the first fluid. The duct (9) is spaced from the pressure vessel (1) and is surrounded with thermal insulation (23). An opening in the duct (9) equalizes the pressure between the inside and the outside of the duct (9) which is also supported against expansion caused by the pressure inside the duct (9) exceeding the pressure outside the duct (9).
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: January 11, 2005
    Assignee: Innogy Plc
    Inventors: Alexander Bruce Wilson, Michael Willoughby Essex Coney, David John Gooch, Birendra Nath, Andrew Powell
  • Publication number: 20030159815
    Abstract: A heat exchanger comprising a pressure vessel (1). A plurality of serpentines (8) convey a fluid to be heated through the pressure vessel (1) in one direction. A duct (9) surrounding the serpentines (8) conveys a second fluid in the opposite direction to give up its heat to the first fluid. The duct (9) is spaced from the pressure vessel (1) and is surrounded with thermal insulation (23). An opening in the duct (9) equalises the pressure between the inside and the outside of the duct (9) which is also supported against expansion caused by the pressure inside the duct (9) exceeding the pressure outside the duct (9).
    Type: Application
    Filed: April 1, 2003
    Publication date: August 28, 2003
    Inventors: Alexandria Bruce Wilson, Michael Willboughby Essex Coney, David John Gooch, Birendra Nath, Andrew Powell
  • Publication number: 20030001275
    Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A-X-Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.
    Type: Application
    Filed: June 14, 2001
    Publication date: January 2, 2003
    Inventors: Carlos Juan Sambucetti, Xiaomeng Chen, Soon-Cheon Seo, Birendra Nath Agarwala, Chao-Kun Hu, Naftali Eliahu Lustig, Stephen Edward Greco
  • Patent number: 6111321
    Abstract: A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventor: Birendra Nath Agarwala