Patents by Inventor Birendra Nath Agarwala

Birendra Nath Agarwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030001275
    Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A-X-Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.
    Type: Application
    Filed: June 14, 2001
    Publication date: January 2, 2003
    Inventors: Carlos Juan Sambucetti, Xiaomeng Chen, Soon-Cheon Seo, Birendra Nath Agarwala, Chao-Kun Hu, Naftali Eliahu Lustig, Stephen Edward Greco
  • Patent number: 6111321
    Abstract: A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventor: Birendra Nath Agarwala