Abstract: A predetermined waveform is generated using a lower frequency clock signal (16) and a higher frequency clock signal (18). The waveform transitions between first and second states (12, 14) in synchrony with timing signals (18-1 to 18-11) of the higher frequency clock signal (18). The higher frequency clock is operated if the waveform will transition between the first and second states (12, 14) before the next timing signal (16-2) of the lower frequency clock. The higher frequency clock is powered down if the waveform will not transition between the first and second states (12, 14) before the next timing signal (16-3) of the lower frequency clock. The predetermined waveform can thus be generated having higher resolution but with lower power consumption.

Abstract: A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.

Abstract: A predetermined waveform is generated using a lower frequency clock signal (16) and a higher frequency clock signal (18). The waveform transitions between first and second states (12, 14) in synchrony with timing signals (18-1 to 18-11) of the higher frequency clock signal (18). The higher frequency clock is operated if the waveform will transition between the first and second states (12, 14) before the next timing signal (16-2) of the lower frequency clock. The higher frequency clock is powered down if the waveform will not transition between the first and second states (12, 14) before the next timing signal (16-3) of the lower frequency clock. The predetermined waveform can thus be generated having higher resolution but with lower power consumption.

Abstract: An interface controller (2) is operated to give one of a plurality of predetermined outputs. An input signal (211) is received and a duration of said input signal is compared with a first and/or second threshold duration. A first output is generated if said input signal duration is shorter than said first threshold duration. A second output is generated if said input signal duration is longer than said first threshold duration but shorter than said second threshold duration. A third output is generated if said input signal duration is longer than said second threshold duration.

Abstract: A programmable radio communication system comprises a transmitter (1) and a receiver (2). The transmitter comprises radio transmitting means (5) and processing means (3).

Abstract: A programmable radio communication system comprises a transmitter (1) and a receiver (2). The transmitter comprises radio transmitting means (5) and processing means (3).

Abstract: A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.