Abstract: When synchronous communication systems such as SONET (synchronous optical network) need to change data formats, the resulting periodically discontinuous clock signal associated with the data after overhead has been removed, has to be smoothed to a periodically continuous clock signal associated with resynchronized output data. The SONET format employs pointers which may be described as large phase hit error signals relative the clock signal. The present invention illustrates a technique for slowly integrating the large phase hit error signals into the clock smoothing process so that jitter in the smoothed clock output is held below previously obtainable limits. This is accomplished by high-pass filtering the large phase hit signal and summing it with the periodically discontinuous clock before applying it to a second order type 2 low-pass filter system which filter system employs phase locked loop synchronizing techniques.

Abstract: A high-pass filter which provides a digital word output indicative of a high-pass filter function of the quantity of logic "1" inputs to the counter. The output of a counter is low-pass filtered and applied in conjunction with a bias signal to a second counter which counts clock inputs from a value determined by the count input from the low-pass filter to a predetermined limit and outputs a feedback pulse to be used by the first counter in opposition to a second bias string of pulses where the second bias string of pulses and the feedback signal have substantially the same frequency of pulse rate under steady state conditions of the filter.

Abstract: A variable frequency oscillator which is completely digital and does not use high frequency parts higher than 50 megahertz and yet operates at 50 MHz. Variable frequency is obtained by increment and decrement inputs supplied to a control block which selects between selected phase holding signal inputs obtained from an external source. The output pulse is returned to the control mechanism to start the cycle over. Internal to the control is an algorithm or control sequence which uses a make-before-break approach to prevent glitches which tend to occur during change of phase.

Abstract: A digital implementation of an analog phase detector is illustrated, wherein the novel aspect is the use of a low speed clock, which is passed through a delay line to provide ten different phases of clock signal. The circuitry is used to generate digital numbers on a basis similar to the pulses in an analog equivalent, which numbers are summed to provide a phase detected output.

Abstract: A digital clock recovery circuit is presented which uses a delay line to produce a plurality of delayed sample signals. The sample signals are used to sample incoming data in a phase detector and the resultant sampled data is then resampled by the tentatively correct apparatus clock output signal. The resampled data provides a direct indication of the phase difference beween the data and the clock and the value can be obtained using a summing circuit. If the summed amount is outside an allowable range of values, a phase altering signal is supplied to an oscillator to change the phase of the apparatus clock output signal.

Abstract: A digital phase locked loop to function as a stable reference clock given a gapped, or pulse stuffed, input clock signal which may have a frequency offset relative to the nominal specified frequency and a phase jitter relative to the average frequency of the input signal, the digital phase locked loop comprising an input synchronizer for synchronizing the input clock signal to a stable high frequency reference clock. The output of the input synchronizer increments a write counter and resets a phase counter to zero at the begininning of each cycle of the input clock signal. The outputs of the write counter and the phase counter are sampled by a sampling circuit which interprets the sampled data in two's complement form.

Abstract: Phase quantizer apparatus in an all digital phase locked loop to provide a two-part digital number representing the phase of the input signal (a noncontinuous pulse train) relative to the output signal of the all digital phase locked loop. The phase quantizer comprises a write counter (modulo m counter) and a phase counter (modulo n counter) which receive the noncontinuous pulse train as an input signal. The leading pulse edge in the noncontinuous pulse train increments the write counter and resets the phase counter. The write counter comprises a binary counter and a conversion circuit. The binary counter portion of the write counter was being used and is still being used in the digital communications system to provide address information to the elastic buffer to read data into predetermined storage locations in the elastic buffer.

Abstract: An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2.sup.m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2.sup.m counter and increments same. The 2.sup.m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2.sup.m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2.sup.

Abstract: A digital circuit which ascertains the middle of a digital pulse by first determining its total length through digital logic means in combination with a digital signal delay means, and uses this information to operate a state machine (or sequencer), which will assume that data clocks occur at the time of the last received valid data pulse until new logic "1" data is received, and at this time can be resynchronized or phase-locked if there is a time discrepancy between recently received data and the status of the state machine.