Patents by Inventor Blake C. Lin
Blake C. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11758711Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.Type: GrantFiled: March 17, 2022Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-Hua Wang, Chieh-Jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
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Publication number: 20220208770Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.Type: ApplicationFiled: March 17, 2022Publication date: June 30, 2022Applicant: Intel CorporationInventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-Jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
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Patent number: 11329047Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.Type: GrantFiled: April 18, 2018Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
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Patent number: 11024356Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: September 9, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Publication number: 20210098373Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Juan G. ALZATE VINASCO, Chieh-Jen KU, Shem O. OGADHOH, Allen B. GARDINER, Blake C. LIN, Yih WANG, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI
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Publication number: 20200020378Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: ApplicationFiled: September 9, 2019Publication date: January 16, 2020Applicant: Intel CorporationInventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
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Publication number: 20190326296Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Applicant: Intel CorporationInventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
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Patent number: 10438640Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: August 1, 2018Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Publication number: 20190305081Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Applicant: INTEL CORPORATIONInventors: Travis W. LaJoie, Abhishek A. Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem O. Ogadhoh, Allen B. Gardiner, Blake C. Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
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Publication number: 20180342277Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: ApplicationFiled: August 1, 2018Publication date: November 29, 2018Applicant: Intel CorporationInventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
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Patent number: 10068628Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: June 28, 2013Date of Patent: September 4, 2018Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Patent number: 9865322Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: GrantFiled: September 29, 2016Date of Patent: January 9, 2018Assignee: INTEL CORPORATIONInventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
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Publication number: 20170018298Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
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Patent number: 9478273Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: GrantFiled: October 31, 2013Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
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Publication number: 20160125927Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: ApplicationFiled: June 28, 2013Publication date: May 5, 2016Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
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Publication number: 20150117095Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang