Abstract: The present invention relates to reactor tubes packed with a catalyst system employed to deliberately bias process gas flow toward the hot tube segment and away from the cold segment in order to reduce the circumferential tube temperature variation.

Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Abstract: The present invention provides a method for tackling the repelling of hammering during pipe pile driving. The technical scheme of the present invention includes: when repelling of hammering occurs in the process of piling through a sand layer, drill holes downwardly around and/or inside the pipe pile, and jet high-pressure water to the sand layer below to cut and disturb the sand layer.

Abstract: Steam-hydrocarbon reforming reactor with a reformer tube containing ceramic-supported catalyst pellets and metal foam particles. The ceramic-supported catalyst pellets have a porous support comprising one or more of alumina, calcium aluminate, and magnesium aluminate. The metal foam particles comprise Fe and/or Ni. The ceramic-supported catalyst pellets and metal foam particles may be layered or interspersed.

Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Abstract: The present invention provides a method for tackling the repelling of hammering during pipe pile driving, which is of simply structure and can be carried out easily. The technical scheme of the present invention comprises: When repelling of hammering occurs in the process of piling through a sand layer, drill holes downwardly around and/or inside the pipe pile, and jet high-pressure water to the sand layer below to cut and disturb the sand layer, which consequently decreases the soil resistance to the pipe pile and increases the driveability. The present invention is applied to geotechnical engineering.

Abstract: Steam-hydrocarbon reforming reactor with a reformer tube containing ceramic-supported catalyst pellets and metal foam particles. The ceramic-supported catalyst pellets have a porous support comprising one or more of alumina, calcium aluminate, and magnesium aluminate. The metal foam particles comprise Fe and/or Ni. The ceramic-supported catalyst pellets and metal foam particles may be layered or interspersed.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Method of operating a catalytic steam-hydrocarbon reformer where the steam flow rate at which carbon forms on the inner wall of a catalyst-containing reformer tube is determined, and the steam flow rate to the catalytic steam-hydrocarbon reformer is controlled responsive to the determined steam flow rate at which carbon forms on the inner wall of the catalyst-containing reformer tube.

Abstract: An adsorption vessel comprising a packed bed region of adsorbent particles contiguously arranged, comprising a perforated adsorbent particles, a gas separation process using the perforated adsorbent particles, and methods for making the perforated adsorbent particles. The perforated adsorbent particles each comprise an adsorbent material where the perforated adsorbent particles each have at least 10 channels extending through the particle. The equivalent diameter of the channels may range from 0.05 mm to 1.5 mm, and the void fraction of the channels may range from 0.05 to 0.5.

Abstract: An adsorption vessel comprising a packed bed region of adsorbent particles contiguously arranged comprising a perforated adsorbent particles, a gas separation process using the perforated adsorbent particles, and methods for making the perforated adsorbent particles. The perforated adsorbent particles each comprise an adsorbent material where the perforated adsorbent particles each have at least 10 channels extending through the particle. The equivalent diameter of the channels may range from 0.05 mm to 1.5 mm, and the void fraction of the channels may range from 0.05 to 0.5.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: An adsorption vessel comprising a packed bed region of adsorbent particles contiguously arranged, comprising a perforated adsorbent particles, a gas separation process using the perforated adsorbent particles, and methods for making the perforated adsorbent particles. The perforated adsorbent particles each comprise an adsorbent material where the perforated adsorbent particles each have at least 10 channels extending through the particle. The equivalent diameter of the channels may range from 0.05 mm to 1.5 mm, and the void fraction of the channels may range from 0.05 to 0.5.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: A method for generating and check-controlling a network identity identification code in a network electronic identity is provided for the establishment of a unified network identity management and service ecosystem that effectively protects the network application security and identity information privacy of citizens. A server performs initialization and generates and distributes random numbers while receiving and auditing a request to generate a network identity identification code from a client. If the client passes the audit, encryption coding is performed and a network identity identification code is generated and sent to a network electronic identification card through the client. The network electronic identification card performs check processing of the network identity identification code, and feeds back a result to the server. The server stores the network identity identification code into a database, and informs the user.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.