Patents by Inventor Bo-Jr Huang
Bo-Jr Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Patent number: 11715668Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.Type: GrantFiled: July 9, 2021Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Publication number: 20220334558Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: ApplicationFiled: September 30, 2021Publication date: October 20, 2022Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Publication number: 20210335668Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Patent number: 11075116Abstract: The present disclosure relates to an integrated antenna structure. The integrated antenna structure includes a radiator and a ground plane disposed between a semiconductor substrate and the radiator. A conductive structure is separated from the ground plane by the semiconductor substrate. The conductive structure is electrically coupled to the ground plane. The semiconductor substrate has a thickness of less than approximately 100 microns.Type: GrantFiled: June 19, 2020Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Publication number: 20200321248Abstract: The present disclosure relates to an integrated antenna structure. The integrated antenna structure includes a radiator and a ground plane disposed between a semiconductor substrate and the radiator. A conductive structure is separated from the ground plane by the semiconductor substrate. The conductive structure is electrically coupled to the ground plane. The semiconductor substrate has a thickness of less than approximately 100 microns.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Patent number: 10692763Abstract: The present disclosure, in some embodiments, relates to an integrated antenna structure. The structure includes an excitable element and a first ground plane. The first ground plane is disposed between a first surface of a semiconductor substrate and the excitable element. A first line that is normal to the first surface of the semiconductor substrate extends through both the first ground plane and the excitable element. A second ground plane is separated from the first ground plane by the semiconductor substrate. The second ground plane is electrically coupled to the first ground plane.Type: GrantFiled: December 5, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Publication number: 20190109046Abstract: The present disclosure, in some embodiments, relates to an integrated antenna structure. The structure includes an excitable element and a first ground plane. The first ground plane is disposed between a first surface of a semiconductor substrate and the excitable element. A first line that is normal to the first surface of the semiconductor substrate extends through both the first ground plane and the excitable element. A second ground plane is separated from the first ground plane by the semiconductor substrate. The second ground plane is electrically coupled to the first ground plane.Type: ApplicationFiled: December 5, 2018Publication date: April 11, 2019Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Patent number: 10163708Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.Type: GrantFiled: September 20, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Patent number: 10067000Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.Type: GrantFiled: September 16, 2015Date of Patent: September 4, 2018Assignee: MEDIATEK INC.Inventors: Bo-Jr Huang, Yi-Feng Chen, Jia-Wei Fang
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Patent number: 9991879Abstract: A ring oscillator includes a plurality of inverters. A closed loop structure is formed by cascading the inverters. The inverter includes at least one sensitive inverter with a diode-connected transistor. A variation in an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) threshold voltage of the ring oscillator is detected by analyzing the oscillation frequency of the ring oscillator.Type: GrantFiled: April 21, 2016Date of Patent: June 5, 2018Assignee: MEDIATEK INC.Inventor: Bo-Jr Huang
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Patent number: 9904752Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.Type: GrantFiled: December 31, 2015Date of Patent: February 27, 2018Assignee: MEDIATEK INC.Inventors: Zwei-Mei Lee, Bo-Jr Huang, Chi-Jih Shih, Jia-Wei Fang
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Patent number: 9897632Abstract: A monitor circuit for monitoring a CUT (Circuit Under Test) is provided. The monitor circuit includes a power switch and a current meter. The power switch is coupled between a supply voltage and the CUT. The current meter is coupled in parallel with the power switch. The current meter is configured to detect a current through the CUT.Type: GrantFiled: February 3, 2016Date of Patent: February 20, 2018Assignee: MEDIATEK INC.Inventor: Bo-Jr Huang
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Publication number: 20180012799Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.Type: ApplicationFiled: September 20, 2017Publication date: January 11, 2018Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Patent number: 9779990Abstract: Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane.Type: GrantFiled: February 27, 2013Date of Patent: October 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
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Patent number: 9714979Abstract: A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within a beam. The method further includes converting, with a number of diodes connected to a positive voltage supply, an electrical current signal created by the electron beam to a voltage signal, wherein the number of diodes includes a diode stack of multiple diodes. The method further includes extracting, with a digital inverter, a test signal from the voltage signal.Type: GrantFiled: August 22, 2016Date of Patent: July 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Jr Huang, Nan-Hsin Tseng, Yen-Ling Liu
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Publication number: 20170149423Abstract: A ring oscillator includes a plurality of inverters. A closed loop structure is formed by cascading the inverters. The inverter includes at least one sensitive inverter with a diode-connected transistor. A variation in an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) threshold voltage of the ring oscillator is detected by analyzing the oscillation frequency of the ring oscillator.Type: ApplicationFiled: April 21, 2016Publication date: May 25, 2017Inventor: Bo-Jr HUANG
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Publication number: 20160356845Abstract: A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within a beam. The method further includes converting, with a number of diodes connected to a positive voltage supply, an electrical current signal created by the electron beam to a voltage signal, wherein the number of diodes includes a diode stack of multiple diodes. The method further includes extracting, with a digital inverter, a test signal from the voltage signal.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Inventors: Bo-Jr Huang, Nan-Hsin Tseng, Yen-Ling Liu
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Publication number: 20160343796Abstract: A capacitor structure includes first and second interdigitated conductive elements formed over different portions of a semiconductor substrate, and a dielectric layer formed between the first and second interdigitated conductive elements. The first interdigitated conductive element that is formed includes a first base portion and a plurality of first protrusion portions. The second interdigitated conductive element includes a second base portion and a plurality of second protrusion portions. The second protrusion portions of the second interdigitated conductive element are interleaved with the first protrusion portions of the first interdigitated conductive element.Type: ApplicationFiled: May 19, 2016Publication date: November 24, 2016Inventors: Bo-Jr HUANG, Jia-Wei FANG
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Patent number: 9490808Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.Type: GrantFiled: October 29, 2015Date of Patent: November 8, 2016Assignee: MEDIATEK INC.Inventors: Bo-Jr Huang, Jia-Wei Fang