Patents by Inventor Bo-Jyun CHEN

Bo-Jyun CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230189539
    Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.
    Type: Application
    Filed: February 2, 2023
    Publication date: June 15, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
  • Patent number: 11574908
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: February 7, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
  • Patent number: 11481084
    Abstract: A multi-window switching method and a switching system are provided. The multi-window switching method includes following steps: displaying a first window screen provided via a first computer device and a second window screen provided via a second computer device, wherein a first screen boundary of the first window screen is adjacent to a second screen boundary of the second window screen; receiving a control signal provided by an input device to control a position of a cursor on the first window screen or the second window screen; calculating a first moving speed of the input device when the cursor touches the first screen boundary in the first window screen; and determining whether the first moving speed is greater than or equal to a preset speed threshold to decide whether the cursor is displayed in the second window screen.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 25, 2022
    Assignee: Aten International Co., Ltd.
    Inventors: Hao-Jun Chen, Bo-Jyun Chen
  • Publication number: 20220244859
    Abstract: A data transmission method, applied to a data transmission device connected to a first host and a second host, comprising: (a) activating a console of the first host via a trigger operation and acquiring a source path of target data in the first host; (b) acquiring the target data from the source path and copying the target data to a storage circuit inside or outside the data transmission device; and (c) copying the target data from the storage circuit to the second host.
    Type: Application
    Filed: January 13, 2022
    Publication date: August 4, 2022
    Applicant: ATEN INTERNATIONAL CO., LTD.
    Inventors: Chia-Chang Hsu, Bo-Jyun Chen
  • Publication number: 20220093601
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
  • Publication number: 20210382603
    Abstract: A multi-window switching method and a switching system are provided. The multi-window switching method includes following steps: displaying a first window screen provided via a first computer device and a second window screen provided via a second computer device, wherein a first screen boundary of the first window screen is adjacent to a second screen boundary of the second window screen; receiving a control signal provided by an input device to control a position of a cursor on the first window screen or the second window screen; calculating a first moving speed of the input device when the cursor touches the first screen boundary in the first window screen; and determining whether the first moving speed is greater than or equal to a preset speed threshold to decide whether the cursor is displayed in the second window screen.
    Type: Application
    Filed: May 7, 2021
    Publication date: December 9, 2021
    Applicant: Aten International Co., Ltd.
    Inventors: Hao-Jun Chen, Bo-Jyun Chen
  • Patent number: 11195835
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 7, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
  • Publication number: 20210202484
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN