Patents by Inventor Bo-Mi Lee

Bo-Mi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10103318
    Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 16, 2018
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.
    Inventors: Daisuke Watanabe, Yang Kon Kim, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Guk Cheon Kim, Bo Mi Lee, Won Joon Choi
  • Patent number: 9991313
    Abstract: According to one embodiment, a magnetic memory includes a first magnetic layer, a second magnetic layer, a non-magnetic intermediate layer provided between the first magnetic layer and the second magnetic layer and an underlying layer provided on an opposite side of the first magnetic layer with respect to the intermediate layer, and the underlying layer contains AlN of a hcp structure.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 5, 2018
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX, INC.
    Inventors: Daisuke Watanabe, Makoto Nagamine, Youngmin Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada, Yang Kon Kim, Bo Mi Lee, Guk Cheon Kim, Won Joon Choi, Ki Seon Park
  • Publication number: 20180130512
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
  • Publication number: 20180130945
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Patent number: 9865319
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.
    Type: Grant
    Filed: September 6, 2015
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
  • Patent number: 9865806
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Publication number: 20170344476
    Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.
    Type: Application
    Filed: August 11, 2017
    Publication date: November 30, 2017
    Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
  • Patent number: 9780297
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are formed on the sidewall of the variable resistance element.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: October 3, 2017
    Assignee: SK hynix Inc.
    Inventors: Bo-Mi Lee, Cha-Deok Dong
  • Patent number: 9734060
    Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 15, 2017
    Assignee: SK hynix Inc.
    Inventors: Cha-Deok Dong, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim
  • Patent number: 9722172
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 1, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim
  • Publication number: 20170200487
    Abstract: Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.
    Type: Application
    Filed: March 24, 2017
    Publication date: July 13, 2017
    Inventors: Guk-Cheon Kim, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Yang-Kon Kim
  • Publication number: 20170117457
    Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes a magnetic tunnel junction (MTJ) structure including: a free layer having a changeable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer includes a CoFeAlB alloy.
    Type: Application
    Filed: May 25, 2016
    Publication date: April 27, 2017
    Inventors: Seung-Mo Noh, Yang-Kon Kim, Ku-Youl Jung, Bo-Mi Lee
  • Publication number: 20170069837
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Application
    Filed: November 17, 2016
    Publication date: March 9, 2017
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Publication number: 20170062712
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 2, 2017
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 9543843
    Abstract: There is provided a power supply device having a primary side and a secondary side isolated from each other. The power supply device includes: a power supply unit converting power from the primary side to output the converted power to the secondary side; a control unit located on the secondary side and acquiring control information on the power supply unit based on a voltage output from the power supply unit; and a delivery unit delivering the control information to the primary side, the delivery unit including a Y-capacitor that provides an EMI noise path between the primary side and the secondary side.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 10, 2017
    Assignee: SOLUM CO., LTD.
    Inventors: Tae Won Heo, Hwan Cho, Jeong Gyu Lim, Sang Kyoo Han, Young Seung Noh, Bo Mi Lee
  • Publication number: 20160380182
    Abstract: According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Applicants: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Daisuke WATANABE, Yang Kon KIM, Makoto NAGAMINE, Youngmin EEH, Koji UEDA, Toshihiko NAGASE, Kazuya SAWADA, Guk Cheon KIM, Bo Mi LEE, Won Joon CHOI
  • Patent number: 9529714
    Abstract: An electronic device includes a semiconductor memory, and the semiconductor memory includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a ferromagnetic material with molybdenum (Mo) added thereto.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: December 27, 2016
    Assignees: SK Hynix Inc., Kabushiki Kaisha Toshiba
    Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Daisuke Watanabe, Makoto Nagamine, Young-Min Eeh, Koji Ueda, Toshihiko Nagase, Kazuya Sawada
  • Patent number: 9502639
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 22, 2016
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh
  • Publication number: 20160180905
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.
    Type: Application
    Filed: September 6, 2015
    Publication date: June 23, 2016
    Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
  • Publication number: 20160181514
    Abstract: Disclosed are an electronic device comprising a semiconductor memory and a method for fabricating the same, which enable the characteristics of a variable resistance element to be improved. The electronic device includes a semiconductor memory. The semiconductor memory includes a variable resistance element including a stack of a pinned layer, a tunnel barrier layer and a variable layer. The variable layer may include a material layer having a standard electrode potential higher than that of Fe. According to the electronic device including the semiconductor memory and the method for fabricating the same according to the implementation of the disclosed technology, the characteristics of the variable resistance element may be improved.
    Type: Application
    Filed: June 30, 2015
    Publication date: June 23, 2016
    Inventors: Guk-Cheon Kim, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Yang-Kon Kim