Patents by Inventor Bo Shu
Bo Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240172476Abstract: Disclosed is a display substrate including first, second, third, and fourth sub-pixels; at least one sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes a drive transistor; there is a first overlapping region between an orthographic projection of an anode of a light emitting device in the third sub-pixel on a base substrate and an orthographic projection of a gate electrode of a drive transistor in the third sub-pixel on the base substrate; there is no overlapping region or there is a second overlapping region between an orthographic projection of an anode of a light emitting device in the fourth sub-pixel on the base substrate and an orthographic projection of a gate electrode of a drive transistor in the fourth sub-pixel on the base substrate, an area of the second overlapping region is smaller than an area of the first overlapping region.Type: ApplicationFiled: July 8, 2021Publication date: May 23, 2024Inventors: Rong WANG, Xiaoqing SHU, Mengmeng DU, Bo ZHANG, Xiangdan DONG
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Patent number: 11990545Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: GrantFiled: October 19, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
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Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Patent number: 11990547Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.Type: GrantFiled: September 27, 2020Date of Patent: May 21, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
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Patent number: 11894425Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.Type: GrantFiled: February 6, 2023Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
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Publication number: 20230387107Abstract: A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: YUAN-CHENG YANG, YUN-CHI WU, TSU-HSIU PERNG, SHIH-JUNG TU, CHENG-BO SHU, CHIA-CHEN CHANG
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Publication number: 20230320089Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: ApplicationFiled: June 2, 2023Publication date: October 5, 2023Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Publication number: 20230282742Abstract: An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.Type: ApplicationFiled: May 4, 2023Publication date: September 7, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Bo SHU, Yun-Chi WU
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Patent number: 11711917Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: GrantFiled: August 16, 2021Date of Patent: July 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Patent number: 11688805Abstract: A method for forming an integrated circuit structure is provided. The method includes forming a gate dielectric layer over a semiconductor substrate; depositing a first gate electrode layer over the gate dielectric layer; etching the first gate electrode layer to form a gate electrode over the gate dielectric layer; forming a drift region in the semiconductor substrate; depositing a dielectric layer over the gate dielectric layer and the gate electrode, in which the dielectric layer has a first portion alongside a first sidewall of the gate electrode; depositing a second gate electrode layer over the dielectric layer; etching the second gate electrode layer to form a field plate electrode alongside the first portion of the dielectric layer; and forming source/drain features in the semiconductor substrate.Type: GrantFiled: May 28, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Bo Shu, Yun-Chi Wu
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Publication number: 20230187499Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Yun-Chi WU, Tsung-Yu YANG, Cheng-Bo SHU, Chien Hung LIU
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Publication number: 20230109273Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
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Publication number: 20230040514Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: ApplicationFiled: October 19, 2022Publication date: February 9, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu PERNG, Yun-Chi WU, Chia-Chen CHANG, Cheng-Bo SHU, Jyun-Guan JHOU, Pei-Lun WANG
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Patent number: 11575008Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.Type: GrantFiled: November 16, 2020Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
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Patent number: 11532637Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.Type: GrantFiled: December 23, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
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Publication number: 20220384637Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu PERNG, Yun-Chi WU, Chia-Chen CHANG, Cheng-Bo SHU, Jyun-Guan JHOU, Pei-Lun WANG
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Publication number: 20220384642Abstract: A method for forming an integrated circuit structure is provided. The method includes forming a gate dielectric layer over a semiconductor substrate; depositing a first gate electrode layer over the gate dielectric layer; etching the first gate electrode layer to form a gate electrode over the gate dielectric layer; forming a drift region in the semiconductor substrate; depositing a dielectric layer over the gate dielectric layer and the gate electrode, in which the dielectric layer has a first portion alongside a first sidewall of the gate electrode; depositing a second gate electrode layer over the dielectric layer; etching the second gate electrode layer to form a field plate electrode alongside the first portion of the dielectric layer; and forming source/drain features in the semiconductor substrate.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Bo SHU, Yun-Chi WU
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Patent number: 11508843Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.Type: GrantFiled: May 27, 2021Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang
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Publication number: 20220293799Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: ApplicationFiled: May 26, 2022Publication date: September 15, 2022Inventors: Cheng-Bo SHU, Yun-Chi WU, Chung-Jen HUANG
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Patent number: 11424261Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: GrantFiled: December 10, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu