Abstract: A light-emitting element comprises a first semiconductor layer, an active layer provided on the first semiconductor layer, a second semiconductor layer provided on the active layer, an electrode layer provided on the second semiconductor layer, and an insulating film around outer peripheral surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer, wherein the active layer includes a cover layer including a plurality of quantum dots, and the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer are sequentially stacked in one direction to form a shape of a rod.

Abstract: This application relates to solid forms and salt forms of the PD-1/PD-L1 inhibitor 4,4?-(((((2,2?-dichloro-[1,1?-biphenyl]-3,3?-diyl)bis(azanediyl))bis(carbonyl))bis(1-methyl-1,4,6,7-tetrahydro-5H-imidazo[4,5-c]pyridine-2,5-diyl))bis(ethane-2,1-diyl))bis(bicyclo[2.2.1]heptane-1-carboxylic acid), including processes of preparation thereof, where the solid forms and salt forms are useful in the treatment of various diseases including infectious diseases and cancer.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: A method for crystal pulling is provided. The method includes the following. The method includes performing an equal-diameter process. The equal-diameter process is performed as follows. From the first equal-diameter stage to the third equal-diameter stage, the crystal rotation rate is gradually increased after starting at a first initial crystal rotation rate, and then is kept at a constant rotation rate after gradually increasing the crystal rotation rate. The crucible rotation rate is gradually increased from a first initial crucible rotation rate to a maximum crucible rotation rate after starting at the first initial crucible rotation rate in the first equal-diameter stage, the crucible rotation rate is kept at the maximum crucible rotation rate in the second equal-diameter stage, and the crucible rotation rate is gradually decreased after the second equal-diameter stage. The method further includes a cooling process.

Abstract: A battery includes an electrode assembly including a first electrode, a second electrode and a separator between the first electrode and the second electrode wound around a winding axis to define a core and an outer circumferential surface, the first electrode including a first uncoated region in which an active material layer is not coated along a winding direction; a housing accommodating the electrode assembly through an open portion at a lower end thereof; a first current collector coupled to the first uncoated region and disposed in the housing; a cap to cover the open portion; and a spacer between the first current collector and the cap and having a height corresponding to a distance between the first current collector and the cap.

Abstract: A flow splitting device for gas reverse circulation drilling, including: an upper joint for connecting with a double-wall drill pipe; an inner tube which is arranged in the upper joint and defines a first passageway in communication with an inner chamber of the double-wall drill pipe, a second passageway in communication with an annular space in the double-wall drill pipe formed between the inner tube and the upper joint; a lower joint, having an upper end fixedly connected with the upper joint and a lower end for connecting with a drill tool; and a flow guiding member provided between the upper joint and the lower joint. A flexible sealing mechanism is provided outside the upper joint. The flexible sealing mechanism extends radially outward relative to the upper joint and the lower joint to form a sealing contact with a wellbore wall.

Abstract: Systems and methods for image processing are described. Embodiments of the present disclosure receive an image having a plurality of object instances; encode the image to obtain image features; decode the image features to obtain object features; generate object detection information based on the object features using an object detection branch, wherein the object detection branch is trained based on a first training set using a detection loss; generate semantic segmentation information based on the object features using a semantic segmentation branch, wherein the semantic segmentation branch is trained based on a second training set different from the first training set using a semantic segmentation loss; and combine the object detection information and the semantic segmentation information to obtain panoptic segmentation information that indicates which pixels of the image correspond to each of the plurality of object instances.

Abstract: The present disclosure provides a package structure and a method of manufacturing a package. The package structure includes a semiconductor die laterally encapsulated by an encapsulant, a redistribution structure and bumps. The redistribution structure is disposed on the semiconductor die and the encapsulant, and is electrically connected with the at least one semiconductor die. The bumps are disposed on the redistribution structure. The redistribution structure includes dielectric layers and metallic pattern layers sandwiched between the dielectric layers. The redistribution structure includes metallic pads on an outermost dielectric layer of the dielectric layers, and the outmost dielectric layer has undercut cavities beside the metallic pads.

Abstract: A semiconductor structure includes a plurality of composite layers formed on a portion of a substrate. An interlayer dielectric layer is formed on the substrate and the plurality of composite layers. A first gate trench is formed on the interlayer dielectric layer, and a gate sidewall is formed on a side surface of the first gate trench. The composite layer includes stacked channel layers and a second gate trench between neighboring channel layers. The first gate trench and the gate sidewall cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench communicates with the second gate trench. A gate is formed in the first and second gate trenches. The doping region is formed in a channel layer. The source-drain layer is formed in the composite layer on two sides of the gate structure.

Abstract: The present disclosure provides Diels-Alder adducts of chalcone and prenylphenyl moieties capable of modulating the activity of cannabinoid receptors, and to oligomers of flavan-3-ol capable of modulating fat absorption and storage. Such Diels-Alder adducts of chalcone and prenylphenyl moieties or oligomers of flavan-3-ol can optionally be used in combination with other weight management agents, such as anorectic agents, a lipase inhibitors, other cannabinoid receptor modulators, psychotropic agents, insulin sensitizers, stimulants, or satiety agents, as well as to methods of use thereof such as treating or preventing weight gain or obesity, promoting weight loss, appetite suppression, modifying satiety, or the like.

Abstract: Semiconductor structure and formation method are provided. A method of forming a semiconductor structure includes providing a dielectric layer on a substrate, the dielectric layer including a first region and a second region under the first region, the first region including discrete first initial nanowires, and the second region including discrete second initial nanowires; etching the dielectric layer and the first initial nanowires in the first region to form a first opening in the first region, and forming first nanowires from the first initial nanowires; etching the dielectric layer at a bottom of the first opening and the second initial nanowires to form a second opening in the second region, and forming second nanowires from the second initial nanowires; forming a second source/drain layer in the second opening; forming an isolation layer on the second source/drain layer; and forming a first source/drain layer in the first opening.

Abstract: Semiconductor structures and methods for forming the same are provided.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: An authorized access list generation method including: at least one network service providing device registering for an authorized access list notification service with a server, the authorized access list including at least one authorization related record of at least one legitimate user device; the legitimate user device outputting a user ID to the server to log into the server, and directly sending an access request to a target network service provider after logging into the server, and continuing to provide an IP address being used and a device ID to the server to update a corresponding authorization related record; and the target network service providing device comparing the IP address, stored in each authorization related record of the authorized access list, with the IP address of a user device issuing an access request, and rejecting the access request if no matched result is found.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.

Abstract: The present disclosure discloses a shoulder joint prosthesis containing zirconium-niobium alloy on oxidation layer and a preparation method thereof, the preparation method comprises: using zirconium-niobium alloy powder as a raw material, conducting a 3D printing for one-piece molding to obtain an intermediate products of the humeral handle with articular surface and the scapular glenoid plate, and performing Sinter-HIP, cryogenic cooling and surface oxidation to obtain humeral handle with articular surface and scapular glenoid plate. The prosthesis comprises a humeral handle, an articular surface, a humeral head and a scapular glenoid plate, a bone trabeculae is arranged on the outer surface of the upper part of the humeral handle, the upper surface of the scapular glenoid plate and the outer surface of the circular pipe with internal thread.

Abstract: Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Abstract: A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.

Abstract: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.

Abstract: An integrated binocular augmented reality smart glass, which comprises an integrated structure of glass temples, an imaging system, a nose pad, a battery module and a glass frame, and a circuit board processor module and a control system are integrated therein. The integrated binocular augmented reality smart glass has a small volume, a light weight and a strong mobile flexibility and is convenient in usage and interaction, and can be worn stably for a long time under various application scenarios without generating discomfort. The imaging system of the integrated binocular augmented reality smart glass is a multi-layer structure, and comprises filter glasses, display glasses and functional glasses, where the filter glasses and the functional glasses are respectively located at two sides of the display glasses and are mounted on the glass frame.