Patents by Inventor Bo-un Yoon

Bo-un Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for fabricating the same
    Patent number: 9190407
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN
    Publication number: 20150325575
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Application
    Filed: March 5, 2015
    Publication date: November 12, 2015
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20150279991
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Application
    Filed: May 26, 2015
    Publication date: October 1, 2015
    Inventors: Sang-Jine PARK, Bo-Un YOON, Jeong-Nam HAN, Myung-Geun SONG
  • Method of fabricating semiconductor device
    Patent number: 9136135
    Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jik Baek, Ji-Hoon Cha, Bo-Un Yoon, Kwang-Wook Lee, Jeong-Nam Han
  • SEMICONDUCTOR DEVICES INCLUDING TRENCH WALLS HAVING MULTIPLE SLOPES
    Publication number: 20150187946
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Application
    Filed: August 8, 2014
    Publication date: July 2, 2015
    Inventors: Sang-Jine PARK, Bo-Un YOON, Ha-Young JEON, Byung-Kwon CHO, Jeong-Nam HAN
  • METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    Publication number: 20150162197
    Abstract: A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.
    Type: Application
    Filed: October 28, 2014
    Publication date: June 11, 2015
    Inventors: Jae-Jik BAEK, Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Ji-Min Jeong, Ji-Hoon Cha
  • Method of fabricating semiconductor device
    Patent number: 9054210
    Abstract: A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Jine Park, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han, Kee-Sang Kwon, Won-Sang Choi
  • Semiconductor device and method of fabricating the same
    Patent number: 9040415
    Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Byung-Kwon Cho, Ji-Hoon Cha
  • Semiconductor device including dummy gate part and method of fabricating the same
    Patent number: 9035396
    Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
  • Method for fabricating a semiconductor device
    Patent number: 9023704
    Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Young Yoon, Chang-Sun Hwang, Bo-Kyeong Kang, Jae-Seok Kim, Ho-Young Kim, Bo-Un Yoon
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20150097251
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20150056795
    Abstract: A method of manufacturing a semiconductor devices includes providing a semiconductor substrate that includes a channel region. The method includes forming a gate electrode material film including a stepped portion on the channel region. A sacrificial material film that has an etch selectivity that is the same as an etch selectivity of the gate electrode material film is formed. The sacrificial material film is planarized until a top surface of the gate electrode material film is exposed. The stepped portion is reduced by removing an exposed portion of the gate electrode material film.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 26, 2015
    Inventors: Bo-kyeong Kang, Bo-un Yoon, Il-young Yoon, Jae-kwang Choi, Ho-young Kim, Se-jung Park, Jae-seok Kim
  • Methods of forming gates of semiconductor devices
    Patent number: 8962415
    Abstract: Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Won Lee, Bo-Un Yoon, Seung-Jae Lee
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150050793
    Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.
    Type: Application
    Filed: May 23, 2014
    Publication date: February 19, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Jine PARK, Bo-Un YOON, Young-Sang YOUN, Jeong-Nam HAN, Kee-Sang KWON, Doo-Sung YUN, Byung-Kwon CHO, Ji-Hoon CHA
  • Semiconductor device and method for fabricating the same
    Patent number: 8916460
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20140322881
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 30, 2014
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
  • CHEMICAL SUPPLIER, PROCESSING APPARATUS INCLUDING THE CHEMICAL SUPPLIER
    Publication number: 20140231010
    Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Inventors: Sang-Jine PARK, Bo-Un YOON, Jeong-Nam HAN, Kee-Sang KWON, Doo-Sung YUN, Won-Sang CHOI
  • METHODS OF FORMING GATES OF SEMICONDUCTOR DEVICES
    Publication number: 20140235047
    Abstract: Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.
    Type: Application
    Filed: April 29, 2014
    Publication date: August 21, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: JONG-WON LEE, Bo-Un YOON, Seung-Jae LEE
  • METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
    Publication number: 20140227847
    Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 14, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: IL-YOUNG YOON, CHANG-SUN HWANG, BO-KYEONG KANG, JAE-SEOK KIM, HO-YOUNG KIM, BO-UN YOON
  • Methods of Fabricating Semiconductor Devices Including Fin-Shaped Active Regions
    Publication number: 20140227857
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 14, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: YOUNG-SANG YOUN, MYUNG-GEUN SONG, JI-HOON CHA, JAE-JIK BAEK, BO-UN YOON, JEONG-NAM HAN