Abstract: A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.

Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

Abstract: An apparatus for measuring the surface potential and impurity concentration in a semi-conductor body by monitoring the current flowing in a semiconductor body when the body is biased with a ramp voltage above its flat band voltage and summing the monitored current with the ramp voltage biasing the body. The apparatus provides direct measurement of surface potential and impurity concentration in a semiconductor structure and is especially useful in metal insulator semiconductor (MIS) structures.

Abstract: A method is shown for forming ultra fine, deep dielectric isolation in a silicon body. The method involves forming a first layer of material on the silicon body over a first set of alternately designated device regions. A conformal coating is deposited over the first layer and on the silicon body included in a second set of alternately designated device regions and the designated isolation regions. The thickness of the conformal coating is chosen to be substantially the width of the planned isolation between device regions. A second layer is then deposited over the conformal coating. The first layer and conformal coating are composed of different materials.